// SPDX-License-Identifier: GPL-2.0
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/*
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* Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
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*
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* Copyright (C) 2018 Renesas Electronics Europe Limited
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "renesas,r9a06g032";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clocks = <&sysctrl 84>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <1>;
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clocks = <&sysctrl 84>;
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enable-method = "renesas,r9a06g032-smp";
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cpu-release-addr = <0 0x4000c204>;
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};
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};
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ext_jtag_clk: extjtagclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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ext_mclk: extmclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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};
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ext_rgmii_ref: extrgmiiref {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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ext_rtc_clk: extrtcclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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sysctrl: system-controller@4000c000 {
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compatible = "renesas,r9a06g032-sysctrl";
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reg = <0x4000c000 0x1000>;
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status = "okay";
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#clock-cells = <1>;
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clocks = <&ext_mclk>, <&ext_rtc_clk>,
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<&ext_jtag_clk>, <&ext_rgmii_ref>;
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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};
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uart0: serial@40060000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x40060000 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl 146>;
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clock-names = "baudclk";
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status = "disabled";
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};
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gic: gic@44101000 {
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compatible = "arm,cortex-a7-gic", "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x44101000 0x1000>, /* Distributer */
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<0x44102000 0x2000>, /* CPU interface */
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<0x44104000 0x2000>, /* Virt interface control */
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<0x44106000 0x2000>; /* Virt CPU interface */
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interrupts =
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<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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timer {
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compatible = "arm,cortex-a7-timer",
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"arm,armv7-timer";
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interrupt-parent = <&gic>;
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arm,cpu-registers-not-fw-configured;
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always-on;
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interrupts =
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<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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