// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*
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* author:
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* Alpha Lin, alpha.lin@rock-chips.com
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* Randy Li, randy.li@rock-chips.com
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* Ding Wei, leo.ding@rock-chips.com
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*
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*/
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#include <asm/cacheflush.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <linux/regmap.h>
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#include <linux/proc_fs.h>
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#include <linux/nospec.h>
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#include <soc/rockchip/pm_domains.h>
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#include "mpp_debug.h"
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#include "mpp_common.h"
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#include "mpp_iommu.h"
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#define VEPU1_DRIVER_NAME "mpp_vepu1"
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#define VEPU1_SESSION_MAX_BUFFERS 20
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/* The maximum registers number of all the version */
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#define VEPU1_REG_NUM 164
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#define VEPU1_REG_HW_ID_INDEX 0
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#define VEPU1_REG_START_INDEX 0
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#define VEPU1_REG_END_INDEX 163
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#define VEPU1_REG_INT 0x004
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#define VEPU1_REG_INT_INDEX (1)
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#define VEPU1_INT_SLICE BIT(8)
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#define VEPU1_INT_TIMEOUT BIT(6)
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#define VEPU1_INT_BUF_FULL BIT(5)
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#define VEPU1_INT_RESET BIT(4)
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#define VEPU1_INT_BUS_ERROR BIT(3)
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#define VEPU1_INT_RDY BIT(2)
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#define VEPU1_IRQ_DIS BIT(1)
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#define VEPU1_INT_RAW BIT(0)
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#define VEPU1_REG_ENC_EN 0x038
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#define VEPU1_REG_ENC_EN_INDEX (14)
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#define VEPU1_INT_TIMEOUT_EN BIT(31)
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#define VEPU1_INT_SLICE_EN BIT(28)
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#define VEPU1_ENC_START BIT(0)
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#define VEPU1_GET_FORMAT(x) (((x) >> 1) & 0x3)
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#define VEPU1_FORMAT_MASK (0x06)
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#define VEPU1_FMT_RESERVED (0)
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#define VEPU1_FMT_VP8E (1)
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#define VEPU1_FMT_JPEGE (2)
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#define VEPU1_FMT_H264E (3)
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#define VEPU1_REG_CLR_CACHE_BASE 0xc10
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#define to_vepu_task(task) \
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container_of(task, struct vepu_task, mpp_task)
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#define to_vepu_dev(dev) \
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container_of(dev, struct vepu_dev, mpp)
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struct vepu_task {
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struct mpp_task mpp_task;
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enum MPP_CLOCK_MODE clk_mode;
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u32 reg[VEPU1_REG_NUM];
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struct reg_offset_info off_inf;
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u32 irq_status;
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/* req for current task */
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u32 w_req_cnt;
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struct mpp_request w_reqs[MPP_MAX_MSG_NUM];
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u32 r_req_cnt;
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struct mpp_request r_reqs[MPP_MAX_MSG_NUM];
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};
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struct vepu_session_priv {
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struct rw_semaphore rw_sem;
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/* codec info from user */
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struct {
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/* show mode */
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u32 flag;
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/* item data */
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u64 val;
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} codec_info[ENC_INFO_BUTT];
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};
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struct vepu_dev {
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struct mpp_dev mpp;
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struct mpp_clk_info aclk_info;
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struct mpp_clk_info hclk_info;
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#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
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struct proc_dir_entry *procfs;
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#endif
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struct reset_control *rst_a;
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struct reset_control *rst_h;
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};
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static struct mpp_hw_info vepu_v1_hw_info = {
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.reg_num = VEPU1_REG_NUM,
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.reg_id = VEPU1_REG_HW_ID_INDEX,
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.reg_start = VEPU1_REG_START_INDEX,
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.reg_end = VEPU1_REG_END_INDEX,
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.reg_en = VEPU1_REG_ENC_EN_INDEX,
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};
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/*
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* file handle translate information
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*/
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static const u16 trans_tbl_default[] = {
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5, 6, 7, 8, 9, 10, 11, 12, 13, 51
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};
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static const u16 trans_tbl_vp8e[] = {
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5, 6, 7, 8, 9, 10, 11, 12, 13, 16, 17, 26, 51, 52, 58, 59, 71
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};
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static struct mpp_trans_info trans_rk_vepu1[] = {
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[VEPU1_FMT_RESERVED] = {
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.count = 0,
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.table = NULL,
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},
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[VEPU1_FMT_VP8E] = {
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.count = ARRAY_SIZE(trans_tbl_vp8e),
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.table = trans_tbl_vp8e,
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},
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[VEPU1_FMT_JPEGE] = {
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.count = ARRAY_SIZE(trans_tbl_default),
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.table = trans_tbl_default,
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},
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[VEPU1_FMT_H264E] = {
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.count = ARRAY_SIZE(trans_tbl_default),
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.table = trans_tbl_default,
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},
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};
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static int vepu_process_reg_fd(struct mpp_session *session,
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struct vepu_task *task,
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struct mpp_task_msgs *msgs)
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{
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int ret = 0;
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int fmt = VEPU1_GET_FORMAT(task->reg[VEPU1_REG_ENC_EN_INDEX]);
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ret = mpp_translate_reg_address(session, &task->mpp_task,
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fmt, task->reg, &task->off_inf);
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if (ret)
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return ret;
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mpp_translate_reg_offset_info(&task->mpp_task,
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&task->off_inf, task->reg);
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return 0;
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}
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static int vepu_extract_task_msg(struct vepu_task *task,
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struct mpp_task_msgs *msgs)
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{
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u32 i;
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int ret;
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struct mpp_request *req;
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struct mpp_hw_info *hw_info = task->mpp_task.hw_info;
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for (i = 0; i < msgs->req_cnt; i++) {
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u32 off_s, off_e;
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req = &msgs->reqs[i];
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if (!req->size)
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continue;
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switch (req->cmd) {
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case MPP_CMD_SET_REG_WRITE: {
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off_s = hw_info->reg_start * sizeof(u32);
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off_e = hw_info->reg_end * sizeof(u32);
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ret = mpp_check_req(req, 0, sizeof(task->reg),
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off_s, off_e);
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if (ret)
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continue;
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if (copy_from_user((u8 *)task->reg + req->offset,
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req->data, req->size)) {
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mpp_err("copy_from_user reg failed\n");
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return -EIO;
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}
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memcpy(&task->w_reqs[task->w_req_cnt++],
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req, sizeof(*req));
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} break;
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case MPP_CMD_SET_REG_READ: {
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off_s = hw_info->reg_start * sizeof(u32);
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off_e = hw_info->reg_end * sizeof(u32);
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ret = mpp_check_req(req, 0, sizeof(task->reg),
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off_s, off_e);
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if (ret)
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continue;
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memcpy(&task->r_reqs[task->r_req_cnt++],
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req, sizeof(*req));
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} break;
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case MPP_CMD_SET_REG_ADDR_OFFSET: {
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mpp_extract_reg_offset_info(&task->off_inf, req);
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} break;
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default:
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break;
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}
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}
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mpp_debug(DEBUG_TASK_INFO, "w_req_cnt %d, r_req_cnt %d\n",
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task->w_req_cnt, task->r_req_cnt);
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return 0;
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}
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static void *vepu_alloc_task(struct mpp_session *session,
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struct mpp_task_msgs *msgs)
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{
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int ret;
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struct mpp_task *mpp_task = NULL;
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struct vepu_task *task = NULL;
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struct mpp_dev *mpp = session->mpp;
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mpp_debug_enter();
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task = kzalloc(sizeof(*task), GFP_KERNEL);
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if (!task)
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return NULL;
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mpp_task = &task->mpp_task;
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mpp_task_init(session, mpp_task);
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mpp_task->hw_info = mpp->var->hw_info;
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mpp_task->reg = task->reg;
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/* extract reqs for current task */
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ret = vepu_extract_task_msg(task, msgs);
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if (ret)
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goto fail;
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/* process fd in register */
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if (!(msgs->flags & MPP_FLAGS_REG_FD_NO_TRANS)) {
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ret = vepu_process_reg_fd(session, task, msgs);
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if (ret)
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goto fail;
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}
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task->clk_mode = CLK_MODE_NORMAL;
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mpp_debug_leave();
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return mpp_task;
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fail:
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mpp_task_dump_mem_region(mpp, mpp_task);
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mpp_task_dump_reg(mpp, mpp_task);
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mpp_task_finalize(session, mpp_task);
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kfree(task);
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return NULL;
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}
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static int vepu_run(struct mpp_dev *mpp,
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struct mpp_task *mpp_task)
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{
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u32 i;
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u32 reg_en;
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struct vepu_task *task = to_vepu_task(mpp_task);
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u32 timing_en = mpp->srv->timing_en;
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mpp_debug_enter();
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/* clear cache */
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mpp_write_relaxed(mpp, VEPU1_REG_CLR_CACHE_BASE, 1);
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/* set registers for hardware */
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reg_en = mpp_task->hw_info->reg_en;
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/* First, flush correct encoder format */
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mpp_write_relaxed(mpp, VEPU1_REG_ENC_EN,
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task->reg[reg_en] & VEPU1_FORMAT_MASK);
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/* Second, flush others register */
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for (i = 0; i < task->w_req_cnt; i++) {
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struct mpp_request *req = &task->w_reqs[i];
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int s = req->offset / sizeof(u32);
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int e = s + req->size / sizeof(u32);
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mpp_write_req(mpp, task->reg, s, e, reg_en);
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}
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/* flush tlb before starting hardware */
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mpp_iommu_flush_tlb(mpp->iommu_info);
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/* init current task */
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mpp->cur_task = mpp_task;
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mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
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/* Last, flush start registers */
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wmb();
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mpp_write(mpp, VEPU1_REG_ENC_EN,
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task->reg[reg_en] | VEPU1_ENC_START);
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mpp_task_run_end(mpp_task, timing_en);
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mpp_debug_leave();
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return 0;
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}
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static int vepu_irq(struct mpp_dev *mpp)
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{
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mpp->irq_status = mpp_read(mpp, VEPU1_REG_INT);
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if (!(mpp->irq_status & VEPU1_INT_RAW))
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return IRQ_NONE;
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mpp_write(mpp, VEPU1_REG_INT, 0);
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return IRQ_WAKE_THREAD;
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}
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static int vepu_isr(struct mpp_dev *mpp)
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{
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u32 err_mask;
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struct vepu_task *task = NULL;
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struct mpp_task *mpp_task = mpp->cur_task;
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/* FIXME use a spin lock here */
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if (!mpp_task) {
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dev_err(mpp->dev, "no current task\n");
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return IRQ_HANDLED;
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}
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mpp_time_diff(mpp_task);
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mpp->cur_task = NULL;
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task = to_vepu_task(mpp_task);
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task->irq_status = mpp->irq_status;
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mpp_debug(DEBUG_IRQ_STATUS, "irq_status: %08x\n",
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task->irq_status);
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err_mask = VEPU1_INT_TIMEOUT
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| VEPU1_INT_BUF_FULL
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| VEPU1_INT_BUS_ERROR;
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if (err_mask & task->irq_status)
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atomic_inc(&mpp->reset_request);
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mpp_task_finish(mpp_task->session, mpp_task);
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mpp_debug_leave();
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return IRQ_HANDLED;
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}
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static int vepu_finish(struct mpp_dev *mpp,
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struct mpp_task *mpp_task)
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{
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u32 i;
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u32 s, e;
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struct mpp_request *req;
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struct vepu_task *task = to_vepu_task(mpp_task);
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mpp_debug_enter();
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/* read register after running */
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for (i = 0; i < task->r_req_cnt; i++) {
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req = &task->r_reqs[i];
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s = req->offset / sizeof(u32);
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e = s + req->size / sizeof(u32);
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mpp_read_req(mpp, task->reg, s, e);
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}
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/* revert hack for irq status */
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task->reg[VEPU1_REG_INT_INDEX] = task->irq_status;
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mpp_debug_leave();
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return 0;
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}
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static int vepu_result(struct mpp_dev *mpp,
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struct mpp_task *mpp_task,
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struct mpp_task_msgs *msgs)
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{
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u32 i;
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struct mpp_request *req;
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struct vepu_task *task = to_vepu_task(mpp_task);
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/* FIXME may overflow the kernel */
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for (i = 0; i < task->r_req_cnt; i++) {
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req = &task->r_reqs[i];
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if (copy_to_user(req->data,
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(u8 *)task->reg + req->offset,
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req->size)) {
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mpp_err("copy_to_user reg fail\n");
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return -EIO;
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}
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}
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return 0;
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}
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static int vepu_free_task(struct mpp_session *session,
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struct mpp_task *mpp_task)
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{
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struct vepu_task *task = to_vepu_task(mpp_task);
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mpp_task_finalize(session, mpp_task);
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kfree(task);
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return 0;
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}
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static int vepu_control(struct mpp_session *session, struct mpp_request *req)
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{
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switch (req->cmd) {
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case MPP_CMD_SEND_CODEC_INFO: {
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int i;
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int cnt;
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struct codec_info_elem elem;
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struct vepu_session_priv *priv;
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if (!session || !session->priv) {
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mpp_err("session info null\n");
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return -EINVAL;
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}
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priv = session->priv;
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cnt = req->size / sizeof(elem);
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cnt = (cnt > ENC_INFO_BUTT) ? ENC_INFO_BUTT : cnt;
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mpp_debug(DEBUG_IOCTL, "codec info count %d\n", cnt);
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down_write(&priv->rw_sem);
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for (i = 0; i < cnt; i++) {
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if (copy_from_user(&elem, req->data + i * sizeof(elem), sizeof(elem))) {
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mpp_err("copy_from_user failed\n");
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continue;
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}
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if (elem.type > ENC_INFO_BASE && elem.type < ENC_INFO_BUTT &&
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elem.flag > CODEC_INFO_FLAG_NULL && elem.flag < CODEC_INFO_FLAG_BUTT) {
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elem.type = array_index_nospec(elem.type, ENC_INFO_BUTT);
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priv->codec_info[elem.type].flag = elem.flag;
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priv->codec_info[elem.type].val = elem.data;
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} else {
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mpp_err("codec info invalid, type %d, flag %d\n",
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elem.type, elem.flag);
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}
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}
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up_write(&priv->rw_sem);
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} break;
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default: {
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mpp_err("unknown mpp ioctl cmd %x\n", req->cmd);
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} break;
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}
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return 0;
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}
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static int vepu_free_session(struct mpp_session *session)
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{
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if (session && session->priv) {
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kfree(session->priv);
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session->priv = NULL;
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}
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return 0;
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}
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static int vepu_init_session(struct mpp_session *session)
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{
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struct vepu_session_priv *priv;
|
|
if (!session) {
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mpp_err("session is null\n");
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return -EINVAL;
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}
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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init_rwsem(&priv->rw_sem);
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session->priv = priv;
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return 0;
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}
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|
#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
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static int vepu_procfs_remove(struct mpp_dev *mpp)
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{
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struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
if (enc->procfs) {
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proc_remove(enc->procfs);
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enc->procfs = NULL;
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}
|
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return 0;
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}
|
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static int vepu_dump_session(struct mpp_session *session, struct seq_file *seq)
|
{
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int i;
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struct vepu_session_priv *priv = session->priv;
|
|
down_read(&priv->rw_sem);
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/* item name */
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seq_puts(seq, "------------------------------------------------------");
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seq_puts(seq, "------------------------------------------------------\n");
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seq_printf(seq, "|%8s|", (const char *)"session");
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seq_printf(seq, "%8s|", (const char *)"device");
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for (i = ENC_INFO_BASE; i < ENC_INFO_BUTT; i++) {
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bool show = priv->codec_info[i].flag;
|
|
if (show)
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seq_printf(seq, "%8s|", enc_info_item_name[i]);
|
}
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seq_puts(seq, "\n");
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/* item data*/
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seq_printf(seq, "|%8p|", session);
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seq_printf(seq, "%8s|", mpp_device_name[session->device_type]);
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for (i = ENC_INFO_BASE; i < ENC_INFO_BUTT; i++) {
|
u32 flag = priv->codec_info[i].flag;
|
|
if (!flag)
|
continue;
|
if (flag == CODEC_INFO_FLAG_NUMBER) {
|
u32 data = priv->codec_info[i].val;
|
|
seq_printf(seq, "%8d|", data);
|
} else if (flag == CODEC_INFO_FLAG_STRING) {
|
const char *name = (const char *)&priv->codec_info[i].val;
|
|
seq_printf(seq, "%8s|", name);
|
} else {
|
seq_printf(seq, "%8s|", (const char *)"null");
|
}
|
}
|
seq_puts(seq, "\n");
|
up_read(&priv->rw_sem);
|
|
return 0;
|
}
|
|
static int vepu_show_session_info(struct seq_file *seq, void *offset)
|
{
|
struct mpp_session *session = NULL, *n;
|
struct mpp_dev *mpp = seq->private;
|
|
mutex_lock(&mpp->srv->session_lock);
|
list_for_each_entry_safe(session, n,
|
&mpp->srv->session_list,
|
session_link) {
|
if (session->device_type != MPP_DEVICE_VEPU1)
|
continue;
|
if (!session->priv)
|
continue;
|
if (mpp->dev_ops->dump_session)
|
mpp->dev_ops->dump_session(session, seq);
|
}
|
mutex_unlock(&mpp->srv->session_lock);
|
|
return 0;
|
}
|
|
static int vepu_procfs_init(struct mpp_dev *mpp)
|
{
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
enc->procfs = proc_mkdir(mpp->dev->of_node->name, mpp->srv->procfs);
|
if (IS_ERR_OR_NULL(enc->procfs)) {
|
mpp_err("failed on open procfs\n");
|
enc->procfs = NULL;
|
return -EIO;
|
}
|
|
/* for common mpp_dev options */
|
mpp_procfs_create_common(enc->procfs, mpp);
|
|
mpp_procfs_create_u32("aclk", 0644,
|
enc->procfs, &enc->aclk_info.debug_rate_hz);
|
mpp_procfs_create_u32("session_buffers", 0644,
|
enc->procfs, &mpp->session_max_buffers);
|
/* for show session info */
|
proc_create_single_data("sessions-info", 0444,
|
enc->procfs, vepu_show_session_info, mpp);
|
|
return 0;
|
}
|
#else
|
static inline int vepu_procfs_remove(struct mpp_dev *mpp)
|
{
|
return 0;
|
}
|
|
static inline int vepu_procfs_init(struct mpp_dev *mpp)
|
{
|
return 0;
|
}
|
|
static inline int vepu_dump_session(struct mpp_session *session, struct seq_file *seq)
|
{
|
return 0;
|
}
|
#endif
|
|
static int vepu_init(struct mpp_dev *mpp)
|
{
|
int ret;
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_VEPU1];
|
|
/* Get clock info from dtsi */
|
ret = mpp_get_clk_info(mpp, &enc->aclk_info, "aclk_vcodec");
|
if (ret)
|
mpp_err("failed on clk_get aclk_vcodec\n");
|
ret = mpp_get_clk_info(mpp, &enc->hclk_info, "hclk_vcodec");
|
if (ret)
|
mpp_err("failed on clk_get hclk_vcodec\n");
|
/* Set default rates */
|
mpp_set_clk_info_rate_hz(&enc->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ);
|
|
/* Get reset control from dtsi */
|
enc->rst_a = mpp_reset_control_get(mpp, RST_TYPE_A, "video_a");
|
if (!enc->rst_a)
|
mpp_err("No aclk reset resource define\n");
|
enc->rst_h = mpp_reset_control_get(mpp, RST_TYPE_H, "video_h");
|
if (!enc->rst_h)
|
mpp_err("No hclk reset resource define\n");
|
|
return 0;
|
}
|
|
static int vepu_clk_on(struct mpp_dev *mpp)
|
{
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
mpp_clk_safe_enable(enc->aclk_info.clk);
|
mpp_clk_safe_enable(enc->hclk_info.clk);
|
|
return 0;
|
}
|
|
static int vepu_clk_off(struct mpp_dev *mpp)
|
{
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
mpp_clk_safe_disable(enc->aclk_info.clk);
|
mpp_clk_safe_disable(enc->hclk_info.clk);
|
|
return 0;
|
}
|
|
static int vepu_set_freq(struct mpp_dev *mpp,
|
struct mpp_task *mpp_task)
|
{
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
struct vepu_task *task = to_vepu_task(mpp_task);
|
|
mpp_clk_set_rate(&enc->aclk_info, task->clk_mode);
|
|
return 0;
|
}
|
|
static int vepu_reduce_freq(struct mpp_dev *mpp)
|
{
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
mpp_clk_set_rate(&enc->aclk_info, CLK_MODE_REDUCE);
|
|
return 0;
|
}
|
|
static int vepu_reset(struct mpp_dev *mpp)
|
{
|
struct vepu_dev *enc = to_vepu_dev(mpp);
|
|
if (enc->rst_a && enc->rst_h) {
|
/* Don't skip this or iommu won't work after reset */
|
mpp_pmu_idle_request(mpp, true);
|
mpp_safe_reset(enc->rst_a);
|
mpp_safe_reset(enc->rst_h);
|
udelay(5);
|
mpp_safe_unreset(enc->rst_a);
|
mpp_safe_unreset(enc->rst_h);
|
mpp_pmu_idle_request(mpp, false);
|
}
|
mpp_write(mpp, VEPU1_REG_ENC_EN, 0);
|
|
return 0;
|
}
|
|
static struct mpp_hw_ops vepu_v1_hw_ops = {
|
.init = vepu_init,
|
.clk_on = vepu_clk_on,
|
.clk_off = vepu_clk_off,
|
.set_freq = vepu_set_freq,
|
.reduce_freq = vepu_reduce_freq,
|
.reset = vepu_reset,
|
};
|
|
static struct mpp_dev_ops vepu_v1_dev_ops = {
|
.alloc_task = vepu_alloc_task,
|
.run = vepu_run,
|
.irq = vepu_irq,
|
.isr = vepu_isr,
|
.finish = vepu_finish,
|
.result = vepu_result,
|
.free_task = vepu_free_task,
|
.ioctl = vepu_control,
|
.init_session = vepu_init_session,
|
.free_session = vepu_free_session,
|
.dump_session = vepu_dump_session,
|
};
|
|
static const struct mpp_dev_var vepu_v1_data = {
|
.device_type = MPP_DEVICE_VEPU1,
|
.hw_info = &vepu_v1_hw_info,
|
.trans_info = trans_rk_vepu1,
|
.hw_ops = &vepu_v1_hw_ops,
|
.dev_ops = &vepu_v1_dev_ops,
|
};
|
|
static const struct of_device_id mpp_vepu1_dt_match[] = {
|
{
|
.compatible = "rockchip,vpu-encoder-v1",
|
.data = &vepu_v1_data,
|
},
|
{},
|
};
|
|
static int vepu_probe(struct platform_device *pdev)
|
{
|
int ret = 0;
|
struct device *dev = &pdev->dev;
|
struct vepu_dev *enc = NULL;
|
struct mpp_dev *mpp = NULL;
|
const struct of_device_id *match = NULL;
|
|
dev_info(dev, "probe device\n");
|
enc = devm_kzalloc(dev, sizeof(struct vepu_dev), GFP_KERNEL);
|
if (!enc)
|
return -ENOMEM;
|
|
mpp = &enc->mpp;
|
platform_set_drvdata(pdev, enc);
|
|
if (pdev->dev.of_node) {
|
match = of_match_node(mpp_vepu1_dt_match, pdev->dev.of_node);
|
if (match)
|
mpp->var = (struct mpp_dev_var *)match->data;
|
}
|
|
ret = mpp_dev_probe(mpp, pdev);
|
if (ret) {
|
dev_err(dev, "probe sub driver failed\n");
|
return -EINVAL;
|
}
|
|
ret = devm_request_threaded_irq(dev, mpp->irq,
|
mpp_dev_irq,
|
mpp_dev_isr_sched,
|
IRQF_SHARED,
|
dev_name(dev), mpp);
|
if (ret) {
|
dev_err(dev, "register interrupter runtime failed\n");
|
return -EINVAL;
|
}
|
|
mpp->session_max_buffers = VEPU1_SESSION_MAX_BUFFERS;
|
vepu_procfs_init(mpp);
|
/* register current device to mpp service */
|
mpp_dev_register_srv(mpp, mpp->srv);
|
dev_info(dev, "probing finish\n");
|
|
return 0;
|
}
|
|
static int vepu_remove(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct vepu_dev *enc = platform_get_drvdata(pdev);
|
|
dev_info(dev, "remove device\n");
|
mpp_dev_remove(&enc->mpp);
|
vepu_procfs_remove(&enc->mpp);
|
|
return 0;
|
}
|
|
static void vepu_shutdown(struct platform_device *pdev)
|
{
|
int ret;
|
int val;
|
struct device *dev = &pdev->dev;
|
struct vepu_dev *enc = platform_get_drvdata(pdev);
|
struct mpp_dev *mpp = &enc->mpp;
|
|
dev_info(dev, "shutdown device\n");
|
|
atomic_inc(&mpp->srv->shutdown_request);
|
ret = readx_poll_timeout(atomic_read,
|
&mpp->task_count,
|
val, val == 0, 20000, 200000);
|
if (ret == -ETIMEDOUT)
|
dev_err(dev, "wait total running time out\n");
|
}
|
|
struct platform_driver rockchip_vepu1_driver = {
|
.probe = vepu_probe,
|
.remove = vepu_remove,
|
.shutdown = vepu_shutdown,
|
.driver = {
|
.name = VEPU1_DRIVER_NAME,
|
.of_match_table = of_match_ptr(mpp_vepu1_dt_match),
|
},
|
};
|
EXPORT_SYMBOL(rockchip_vepu1_driver);
|
