// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../mp_precomp.h"
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#include "../phydm_precomp.h"
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void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
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enum odm_rf_radio_path RF_PATH, u32 reg_addr)
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{
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if (addr == 0xffe) {
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ODM_sleep_ms(50);
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} else if (addr == 0xfe) {
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ODM_delay_us(100);
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} else {
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odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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}
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}
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void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_A,
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addr | maskfor_phy_set);
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ODM_RT_TRACE(
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dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
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addr, data);
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}
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void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1001; /* RF_Content: radiob_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_B,
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addr | maskfor_phy_set);
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ODM_RT_TRACE(
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dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
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addr, data);
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}
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void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data)
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{
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odm_write_1byte(dm, addr, data);
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ODM_RT_TRACE(
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dm, ODM_COMP_INIT,
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"===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
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addr, data);
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}
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void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
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u32 data)
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{
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struct dig_thres *dig_tab = &dm->dm_dig_table;
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u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
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u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
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u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
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static bool is_limit;
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if (addr != 0x81c)
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return;
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if (bb_gain_idx > 0x3c) {
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if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) {
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is_limit = true;
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dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
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ODM_RT_TRACE(
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dm, ODM_COMP_DIG,
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"===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
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agc_table_idx,
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dig_tab->big_jump_lmt[agc_table_idx]);
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}
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} else {
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is_limit = false;
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}
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dig_tab->rf_gain_idx = rf_gain_idx;
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}
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void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
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odm_set_bb_reg(dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [AGC_TAB] %08X %08X\n",
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__func__, addr, data);
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}
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void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
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u32 rf_path, u32 tx_num, u32 addr,
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u32 bitmask, u32 data)
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{
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if (addr == 0xfe || addr == 0xffe) {
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ODM_sleep_ms(50);
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} else {
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phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
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addr, bitmask, data);
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}
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ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X %08X\n",
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__func__, addr, bitmask, data);
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}
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void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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if (addr == 0xfe)
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ODM_sleep_ms(50);
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else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else
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odm_set_bb_reg(dm, addr, bitmask, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X\n",
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__func__, addr, data);
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}
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void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
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u8 *band, u8 *bandwidth, u8 *rate_section,
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u8 *rf_path, u8 *channel, u8 *power_limit)
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{
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phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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}
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