/*
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* Structure used by apps whose drivers access SDIO drivers.
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* Pulled out separately so dhdu and wlu can both use it.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _sdiovar_h_
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#define _sdiovar_h_
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#include <typedefs.h>
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typedef struct sdreg {
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int func;
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int offset;
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int value;
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} sdreg_t;
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typedef struct sdreg_64 {
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int func;
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int offset;
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uint64 value;
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} sdreg_64_t;
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/* Common msglevel constants */
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#define SDH_ERROR_VAL 0x0001 /* Error */
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#define SDH_TRACE_VAL 0x0002 /* Trace */
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#define SDH_INFO_VAL 0x0004 /* Info */
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#define SDH_DEBUG_VAL 0x0008 /* Debug */
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#define SDH_DATA_VAL 0x0010 /* Data */
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#define SDH_CTRL_VAL 0x0020 /* Control Regs */
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#define SDH_LOG_VAL 0x0040 /* Enable bcmlog */
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#define SDH_DMA_VAL 0x0080 /* DMA */
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#define SDH_COST_VAL 0x8000 /* Control Regs */
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#define NUM_PREV_TRANSACTIONS 16
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#ifdef BCMSPI
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/* Error statistics for gSPI */
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struct spierrstats_t {
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uint32 dna; /* The requested data is not available. */
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uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */
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uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */
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uint32 f2interrupt; /* OR of all F2 related intr status bits. */
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uint32 f3interrupt; /* OR of all F3 related intr status bits. */
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uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */
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uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */
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uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum
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* (optional)
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*/
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uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */
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uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */
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uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */
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uint32 spicmd[NUM_PREV_TRANSACTIONS];
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};
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#endif /* BCMSPI */
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typedef struct sdio_bus_metrics {
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uint32 active_dur; /* msecs */
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/* Generic */
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uint32 data_intr_cnt; /* data interrupt counter */
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uint32 mb_intr_cnt; /* mailbox interrupt counter */
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uint32 error_intr_cnt; /* error interrupt counter */
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uint32 wakehost_cnt; /* counter for OOB wakehost */
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/* DS forcewake */
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uint32 ds_wake_on_cnt; /* counter for (clock) ON */
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uint32 ds_wake_on_dur; /* duration for (clock) ON) */
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uint32 ds_wake_off_cnt; /* counter for (clock) OFF */
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uint32 ds_wake_off_dur; /* duration for (clock) OFF */
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/* DS_D0 state */
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uint32 ds_d0_cnt; /* counter for DS_D0 state */
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uint32 ds_d0_dur; /* duration for DS_D0 state */
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/* DS_D3 state */
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uint32 ds_d3_cnt; /* counter for DS_D3 state */
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uint32 ds_d3_dur; /* duration for DS_D3 state */
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/* DS DEV_WAKE */
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uint32 ds_dw_assrt_cnt; /* counter for DW_ASSERT */
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uint32 ds_dw_dassrt_cnt; /* counter for DW_DASSERT */
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/* DS mailbox signals */
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uint32 ds_tx_dsreq_cnt; /* counter for tx HMB_DATA_DSREQ */
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uint32 ds_tx_dsexit_cnt; /* counter for tx HMB_DATA_DSEXIT */
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uint32 ds_tx_d3ack_cnt; /* counter for tx HMB_DATA_D3ACK */
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uint32 ds_tx_d3exit_cnt; /* counter for tx HMB_DATA_D3EXIT */
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uint32 ds_rx_dsack_cnt; /* counter for rx SMB_DATA_DSACK */
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uint32 ds_rx_dsnack_cnt; /* counter for rx SMB_DATA_DSNACK */
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uint32 ds_rx_d3inform_cnt; /* counter for rx SMB_DATA_D3INFORM */
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} sdio_bus_metrics_t;
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/* Bus interface info for SDIO */
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typedef struct wl_pwr_sdio_stats {
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uint16 type; /* WL_PWRSTATS_TYPE_SDIO */
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uint16 len; /* Up to 4K-1, top 4 bits are reserved */
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sdio_bus_metrics_t sdio; /* stats from SDIO bus driver */
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} wl_pwr_sdio_stats_t;
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#endif /* _sdiovar_h_ */
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