/*
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* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _SBPCMCIA_H
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#define _SBPCMCIA_H
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/* All the addresses that are offsets in attribute space are divided
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* by two to account for the fact that odd bytes are invalid in
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* attribute space and our read/write routines make the space appear
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* as if they didn't exist. Still we want to show the original numbers
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* as documented in the hnd_pcmcia core manual.
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*/
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/* PCMCIA Function Configuration Registers */
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#define PCMCIA_FCR (0x700 / 2)
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#define FCR0_OFF 0
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#define FCR1_OFF (0x40 / 2)
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#define FCR2_OFF (0x80 / 2)
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#define FCR3_OFF (0xc0 / 2)
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#define PCMCIA_FCR0 (0x700 / 2)
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#define PCMCIA_FCR1 (0x740 / 2)
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#define PCMCIA_FCR2 (0x780 / 2)
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#define PCMCIA_FCR3 (0x7c0 / 2)
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/* Standard PCMCIA FCR registers */
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#define PCMCIA_COR 0
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#define COR_RST 0x80
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#define COR_LEV 0x40
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#define COR_IRQEN 0x04
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#define COR_BLREN 0x01
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#define COR_FUNEN 0x01
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#define PCICIA_FCSR (2 / 2)
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#define PCICIA_PRR (4 / 2)
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#define PCICIA_SCR (6 / 2)
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#define PCICIA_ESR (8 / 2)
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#define PCM_MEMOFF 0x0000
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#define F0_MEMOFF 0x1000
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#define F1_MEMOFF 0x2000
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#define F2_MEMOFF 0x3000
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#define F3_MEMOFF 0x4000
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/* Memory base in the function fcr's */
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#define MEM_ADDR0 (0x728 / 2)
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#define MEM_ADDR1 (0x72a / 2)
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#define MEM_ADDR2 (0x72c / 2)
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/* PCMCIA base plus Srom access in fcr0: */
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#define PCMCIA_ADDR0 (0x072e / 2)
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#define PCMCIA_ADDR1 (0x0730 / 2)
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#define PCMCIA_ADDR2 (0x0732 / 2)
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#define MEM_SEG (0x0734 / 2)
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#define SROM_CS (0x0736 / 2)
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#define SROM_DATAL (0x0738 / 2)
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#define SROM_DATAH (0x073a / 2)
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#define SROM_ADDRL (0x073c / 2)
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#define SROM_ADDRH (0x073e / 2)
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#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
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#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
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/* Values for srom_cs: */
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#define SROM_IDLE 0
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#define SROM_WRITE 1
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#define SROM_READ 2
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#define SROM_WEN 4
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#define SROM_WDS 7
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#define SROM_DONE 8
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/* Fields in srom_info: */
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#define SRI_SZ_MASK 0x03
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#define SRI_BLANK 0x04
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#define SRI_OTP 0x80
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#define SROM16K_BANK_SEL_MASK (3 << 11)
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#define SROM16K_BANK_SHFT_MASK 11
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#define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1)
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#define SROM_PRSNT_MASK 0x1
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#define SROM_SUPPORT_SHIFT_MASK 30
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#define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK)
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#define SROM_SIZE_MASK 0x00000006
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#define SROM_SIZE_2K 2
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#define SROM_SIZE_512 1
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#define SROM_SIZE_128 0
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#define SROM_SIZE_SHFT_MASK 1
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/* CIS stuff */
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/* The CIS stops where the FCRs start */
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#define CIS_SIZE PCMCIA_FCR
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#define CIS_SIZE_12K 1154 /* Maximum h/w + s/w sub region size for 12k OTP */
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/* CIS tuple length field max */
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#define CIS_TUPLE_LEN_MAX 0xff
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/* Standard tuples we know about */
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#define CISTPL_NULL 0x00
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#define CISTPL_END 0xff /* End of the CIS tuple chain */
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#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
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#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
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#define CISTPL_FUNCID 0x21 /* Function identification */
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#define CISTPL_FUNCE 0x22 /* Function extensions */
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#define CISTPL_CFTABLE 0x1b /* Config table entry */
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/* Function identifier provides context for the function extentions tuple */
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#define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */
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/* Function extensions for LANs (assumed for extensions other than SDIO) */
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#define LAN_TECH 1 /* Technology type */
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#define LAN_SPEED 2 /* Raw bit rate */
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#define LAN_MEDIA 3 /* Transmission media */
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#define LAN_NID 4 /* Node identification (aka MAC addr) */
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#define LAN_CONN 5 /* Connector standard */
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/* CFTable */
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#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
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#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
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#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
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/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
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* take one for HNBU, and use "extensions" (a la FUNCE) within it.
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*/
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#define CISTPL_BRCM_HNBU 0x80
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/* Subtypes of BRCM_HNBU: */
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#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
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#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
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#define HNBU_BOARDREV 0x02 /* One byte board revision */
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#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
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* or 9 (sromrev > 1) bytes
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*/
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#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
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#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
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#define HNBU_AA 0x06 /* Antennas available */
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#define HNBU_AG 0x07 /* Antenna gain */
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#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
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#define HNBU_UNUSED 0x09 /* UNUSED (was LEDs) */
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#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
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* in rev 2
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*/
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#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
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#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
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#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
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#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
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#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
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#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
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#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
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* 2 bytes, rev 3.
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*/
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#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
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* 2 bytes, rev 3.
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*/
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#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
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#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
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#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
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#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
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#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
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#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
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#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
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#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
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#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
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#define HNBU_UNUSED2 0x1c /* was LEDs duty cycle */
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#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
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#define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */
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#define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */
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#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
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#define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */
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#define HNBU_REGREV 0x22 /* 1 byte; */
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#define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */
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#define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */
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#define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */
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#define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */
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#define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */
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#define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */
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#define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */
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#define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */
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#define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */
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#define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */
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#define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */
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#define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */
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#define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */
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#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
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#define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */
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#define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */
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#define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */
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#define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */
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#define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */
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#define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */
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#define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */
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#define HNBU_ELNA2G 0x38
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#define HNBU_ELNA5G 0x39
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#define HNBU_TEMPTHRESH 0x3A /* 2 bytes
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* byte1 tempthresh
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* byte2 period(msb 4 bits) | hysterisis(lsb 4 bits)
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*/
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#define HNBU_UUID 0x3B /* 16 Bytes Hex */
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#define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */
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/* POWER PER RATE for SROM V9 */
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#define HNBU_CCKBW202GPO 0x41 /* 2 bytes each
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* CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps)
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* cckbw202gpo cckbw20ul2gpo
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*/
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#define HNBU_LEGOFDMBW202GPO 0x42 /* 4 bytes each
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* OFDM power offsets for 20 MHz Legacy rates
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* (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
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* legofdmbw202gpo legofdmbw20ul2gpo
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*/
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#define HNBU_LEGOFDMBW205GPO 0x43 /* 4 bytes each
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* 5G band: OFDM power offsets for 20 MHz Legacy rates
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* (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
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* low subband : legofdmbw205glpo legofdmbw20ul2glpo
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* mid subband :legofdmbw205gmpo legofdmbw20ul2gmpo
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* high subband :legofdmbw205ghpo legofdmbw20ul2ghpo
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*/
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#define HNBU_MCS2GPO 0x44 /* 4 bytes each
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* mcs 0-7 power-offset. LSB nibble: m0, MSB nibble: m7
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* mcsbw202gpo mcsbw20ul2gpo mcsbw402gpo
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*/
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#define HNBU_MCS5GLPO 0x45 /* 4 bytes each
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* 5G low subband mcs 0-7 power-offset.
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* LSB nibble: m0, MSB nibble: m7
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* mcsbw205glpo mcsbw20ul5glpo mcsbw405glpo
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*/
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#define HNBU_MCS5GMPO 0x46 /* 4 bytes each
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* 5G mid subband mcs 0-7 power-offset.
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* LSB nibble: m0, MSB nibble: m7
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* mcsbw205gmpo mcsbw20ul5gmpo mcsbw405gmpo
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*/
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#define HNBU_MCS5GHPO 0x47 /* 4 bytes each
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* 5G high subband mcs 0-7 power-offset.
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* LSB nibble: m0, MSB nibble: m7
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* mcsbw205ghpo mcsbw20ul5ghpo mcsbw405ghpo
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*/
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#define HNBU_MCS32PO 0x48 /* 2 bytes total
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* mcs-32 power offset for each band/subband.
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* LSB nibble: 2G band, MSB nibble:
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* mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo
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*/
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#define HNBU_LEG40DUPPO 0x49 /* 2 bytes total
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* Additional power offset for Legacy Dup40 transmissions.
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* Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh.
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* LSB nibble: 2G band, MSB nibble: 5G band high subband.
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* leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo
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*/
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#define HNBU_PMUREGS 0x4a /* Variable length (5 bytes for each register)
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* The setting of the ChipCtrl, PLL, RegulatorCtrl, Up/Down Timer and
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* ResourceDependency Table registers.
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*/
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#define HNBU_PATCH2 0x4b /* bootloader TCAM patch addr(4b) & data(4b) pair .
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* This is required for socram rev 15 onwards.
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*/
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#define HNBU_USBRDY 0x4c /* Variable length (upto 5 bytes)
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* This is to indicate the USB/HSIC host controller
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* that the device is ready for enumeration.
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*/
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#define HNBU_USBREGS 0x4d /* Variable length
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* The setting of the devcontrol, HSICPhyCtrl1 and HSICPhyCtrl2
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* registers during the USB initialization.
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*/
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#define HNBU_BLDR_TIMEOUT 0x4e /* 2 bytes used for HSIC bootloader to reset chip
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* on connect timeout.
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* The Delay after USBConnect for timeout till dongle receives
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* get_descriptor request.
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*/
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#define HNBU_USBFLAGS 0x4f
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#define HNBU_PATCH_AUTOINC 0x50
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#define HNBU_MDIO_REGLIST 0x51
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#define HNBU_MDIOEX_REGLIST 0x52
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/* Unified OTP: tupple to embed USB manfid inside SDIO CIS */
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#define HNBU_UMANFID 0x53
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#define HNBU_PUBKEY 0x54 /* 128 byte; publick key to validate downloaded FW */
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#define HNBU_WOWLGPIO 0x55 /* 1 byte bit 7 initial polarity, bit 6..0 gpio pin */
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#define HNBU_MUXENAB 0x56 /* 1 byte to enable mux options */
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#define HNBU_GCI_CCR 0x57 /* GCI Chip control register */
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#define HNBU_FEM_CFG 0x58 /* FEM config */
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#define HNBU_ACPA_C0 0x59 /* ACPHY PA parameters: chain 0 */
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#define HNBU_ACPA_C1 0x5a /* ACPHY PA parameters: chain 1 */
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#define HNBU_ACPA_C2 0x5b /* ACPHY PA parameters: chain 2 */
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#define HNBU_MEAS_PWR 0x5c
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#define HNBU_PDOFF 0x5d
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#define HNBU_ACPPR_2GPO 0x5e /* ACPHY Power-per-rate 2gpo */
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#define HNBU_ACPPR_5GPO 0x5f /* ACPHY Power-per-rate 5gpo */
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#define HNBU_ACPPR_SBPO 0x60 /* ACPHY Power-per-rate sbpo */
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#define HNBU_NOISELVL 0x61
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#define HNBU_RXGAIN_ERR 0x62
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#define HNBU_AGBGA 0x63
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#define HNBU_USBDESC_COMPOSITE 0x64 /* USB WLAN/BT composite descriptor */
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#define HNBU_PATCH_AUTOINC8 0x65 /* Auto increment patch entry for 8 byte patching */
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#define HNBU_PATCH8 0x66 /* Patch entry for 8 byte patching */
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#define HNBU_ACRXGAINS_C0 0x67 /* ACPHY rxgains: chain 0 */
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#define HNBU_ACRXGAINS_C1 0x68 /* ACPHY rxgains: chain 1 */
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#define HNBU_ACRXGAINS_C2 0x69 /* ACPHY rxgains: chain 2 */
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#define HNBU_TXDUTY 0x6a /* Tx duty cycle for ACPHY 5g 40/80 Mhz */
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#define HNBU_USBUTMI_CTL 0x6b /* 2 byte USB UTMI/LDO Control */
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#define HNBU_PDOFF_2G 0x6c
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#define HNBU_USBSSPHY_UTMI_CTL0 0x6d /* 4 byte USB SSPHY UTMI Control */
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#define HNBU_USBSSPHY_UTMI_CTL1 0x6e /* 4 byte USB SSPHY UTMI Control */
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#define HNBU_USBSSPHY_UTMI_CTL2 0x6f /* 4 byte USB SSPHY UTMI Control */
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#define HNBU_USBSSPHY_SLEEP0 0x70 /* 2 byte USB SSPHY sleep */
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#define HNBU_USBSSPHY_SLEEP1 0x71 /* 2 byte USB SSPHY sleep */
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#define HNBU_USBSSPHY_SLEEP2 0x72 /* 2 byte USB SSPHY sleep */
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#define HNBU_USBSSPHY_SLEEP3 0x73 /* 2 byte USB SSPHY sleep */
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#define HNBU_USBSSPHY_MDIO 0x74 /* USB SSPHY INIT regs setting */
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#define HNBU_USB30PHY_NOSS 0x75 /* USB30 NO Super Speed */
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#define HNBU_USB30PHY_U1U2 0x76 /* USB30 PHY U1U2 Enable */
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#define HNBU_USB30PHY_REGS 0x77 /* USB30 PHY REGs update */
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#define HNBU_GPIO_PULL_DOWN 0x78 /* 4 byte GPIO pull down mask */
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#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
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* plus extra info appended.
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*/
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#define HNBU_RESERVED 0x81
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#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */
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#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */
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#define HNBU_ACPAPARAM 0x84 /* ACPHY PAPARAM */
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#define HNBU_ACPA_CCK_C0 0x86 /* ACPHY PA trimming parameters: CCK */
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#define HNBU_ACPA_40 0x87 /* ACPHY PA trimming parameters: 40 */
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#define HNBU_ACPA_80 0x88 /* ACPHY PA trimming parameters: 80 */
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#define HNBU_ACPA_4080 0x89 /* ACPHY PA trimming parameters: 40/80 */
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#define HNBU_SUBBAND5GVER 0x8a /* subband5gver */
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#define HNBU_PAPARAMBWVER 0x8b /* paparambwver */
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#define HNBU_MCS5Gx1PO 0x8c
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#define HNBU_ACPPR_SB8080_PO 0x8d
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#define HNBU_TXBFRPCALS 0x8f /* phy txbf rpcalvars */
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#define HNBU_MACADDR2 0x90 /* (optional) 2nd mac-addr for RSDB chips */
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#define HNBU_ACPA_4X4C0 0x91
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#define HNBU_ACPA_4X4C1 0x92
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#define HNBU_ACPA_4X4C2 0x93
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#define HNBU_ACPA_4X4C3 0x94
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#define HNBU_ACPA_BW20_4X4C0 0x95
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#define HNBU_ACPA_BW40_4X4C0 0x96
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#define HNBU_ACPA_BW80_4X4C0 0x97
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#define HNBU_ACPA_BW20_4X4C1 0x98
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#define HNBU_ACPA_BW40_4X4C1 0x99
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#define HNBU_ACPA_BW80_4X4C1 0x9a
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#define HNBU_ACPA_BW20_4X4C2 0x9b
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#define HNBU_ACPA_BW40_4X4C2 0x9c
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#define HNBU_ACPA_BW80_4X4C2 0x9d
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#define HNBU_ACPA_BW20_4X4C3 0x9e
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#define HNBU_ACPA_BW40_4X4C3 0x9f
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#define HNBU_ACPA_BW80_4X4C3 0xa0
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#define HNBU_ACPA_CCK_C1 0xa1 /* ACPHY PA trimming parameters: CCK */
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#define HNBU_GAIN_CAL_TEMP 0xa2 /* RSSI Cal temperature parameter */
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#define HNBU_RSSI_DELTA_2G_B0 0xa3 /* RSSI Cal parameter for 2G channel group 0 */
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#define HNBU_RSSI_DELTA_2G_B1 0xa4 /* RSSI Cal parameter for 2G channel group 1 */
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#define HNBU_RSSI_DELTA_2G_B2 0xa5 /* RSSI Cal parameter for 2G channel group 2 */
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#define HNBU_RSSI_DELTA_2G_B3 0xa6 /* RSSI Cal parameter for 2G channel group 3 */
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#define HNBU_RSSI_DELTA_2G_B4 0xa7 /* RSSI Cal parameter for 2G channel group 4 */
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#define HNBU_RSSI_CAL_FREQ_GRP_2G 0xa8 /* RSSI Cal parameter for channel group def. */
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#define HNBU_RSSI_DELTA_5GL 0xa9 /* RSSI Cal parameter for 5G low channel */
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#define HNBU_RSSI_DELTA_5GML 0xaa /* RSSI Cal parameter for 5G mid lower channel */
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#define HNBU_RSSI_DELTA_5GMU 0xab /* RSSI Cal parameter for 5G mid upper channel */
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#define HNBU_RSSI_DELTA_5GH 0xac /* RSSI Cal parameter for 5G high channel */
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#define HNBU_ACPA_6G_C0 0xad /* paparams for 6G Core0 */
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#define HNBU_ACPA_6G_C1 0xae /* paparams for 6G Core1 */
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#define HNBU_ACPA_6G_C2 0xaf /* paparams for 6G Core2 */
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/* sbtmstatelow */
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#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
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#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
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/* sbtmstatehigh */
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#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
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#endif /* _SBPCMCIA_H */
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