/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip CIF Driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _RKCIF_HW_H
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#define _RKCIF_HW_H
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#include <linux/mutex.h>
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#include <media/media-device.h>
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#include <media/media-entity.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/videobuf2-v4l2.h>
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#include <media/v4l2-mc.h>
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#include <linux/rk-camera-module.h>
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#include "regs.h"
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#include "version.h"
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#define RKCIF_DEV_MAX 2
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#define RKCIF_HW_DRIVER_NAME "rkcifhw"
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#define RKCIF_MAX_BUS_CLK 8
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#define RKCIF_MAX_RESET 15
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#define write_cif_reg(base, addr, val) \
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writel(val, (addr) + (base))
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#define read_cif_reg(base, addr) \
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readl((addr) + (base))
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#define write_cif_reg_or(base, addr, val) \
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writel(readl((addr) + (base)) | (val), (addr) + (base))
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#define write_cif_reg_and(base, addr, val) \
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writel(readl((addr) + (base)) & (val), (addr) + (base))
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/*
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* add new chip id in tail in time order
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* by increasing to distinguish cif version
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*/
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enum rkcif_chip_id {
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CHIP_PX30_CIF,
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CHIP_RK3128_CIF,
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CHIP_RK3288_CIF,
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CHIP_RK3328_CIF,
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CHIP_RK3368_CIF,
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CHIP_RK1808_CIF,
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CHIP_RV1126_CIF,
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CHIP_RV1126_CIF_LITE,
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CHIP_RK3568_CIF,
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};
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struct rkcif_hw_match_data {
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int chip_id;
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const char * const *clks;
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const char * const *rsts;
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int clks_num;
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int rsts_num;
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const struct cif_reg *cif_regs;
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};
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/*
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* the detecting mode of cif reset timer
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* related with dts property:rockchip,cif-monitor
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*/
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enum rkcif_monitor_mode {
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RKCIF_MONITOR_MODE_IDLE = 0x0,
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RKCIF_MONITOR_MODE_CONTINUE,
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RKCIF_MONITOR_MODE_TRIGGER,
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RKCIF_MONITOR_MODE_HOTPLUG,
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};
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struct rkcif_hw_timer {
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struct timer_list timer;
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spinlock_t timer_lock;
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unsigned long cycle_jif;
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/* unit: us */
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unsigned int run_cnt;
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unsigned int max_run_cnt;
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unsigned int stop_index_of_run_cnt;
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unsigned int monitor_cycle;
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unsigned int err_ref_cnt;
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unsigned int err_time_interval;
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unsigned int is_reset_by_user;
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bool is_running;
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bool has_been_init;
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enum rkcif_monitor_mode monitor_mode;
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enum rkmodule_reset_src reset_src;
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};
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/*
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* struct rkcif_device - ISP platform device
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* @base_addr: base register address
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* @active_sensor: sensor in-use, set when streaming on
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* @stream: capture video device
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*/
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struct rkcif_hw {
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struct device *dev;
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int irq;
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void __iomem *base_addr;
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void __iomem *csi_base;
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struct regmap *grf;
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struct clk *clks[RKCIF_MAX_BUS_CLK];
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int clk_size;
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bool iommu_en;
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struct iommu_domain *domain;
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struct reset_control *cif_rst[RKCIF_MAX_RESET];
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int chip_id;
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const struct cif_reg *cif_regs;
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bool can_be_reset;
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struct rkcif_device *cif_dev[RKCIF_DEV_MAX];
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int dev_num;
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atomic_t power_cnt;
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const struct rkcif_hw_match_data *match_data;
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struct mutex dev_lock;
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struct rkcif_hw_timer hw_timer;
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struct rkcif_reset_info reset_info;
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spinlock_t spin_lock;
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bool reset_work_cancel;
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};
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void rkcif_hw_soft_reset(struct rkcif_hw *cif_hw, bool is_rst_iommu);
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void rkcif_disable_sys_clk(struct rkcif_hw *cif_hw);
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int rkcif_enable_sys_clk(struct rkcif_hw *cif_hw);
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#endif
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