/*
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* Copyright (C) 2010, 2012-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/**
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* @file mali_platform.c
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* Platform specific Mali driver functions for:
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* - Realview Versatile platforms with ARM11 Mpcore and virtex 5.
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* - Versatile Express platforms with ARM Cortex-A9 and virtex 6.
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*/
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#include <linux/platform_device.h>
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#include <linux/version.h>
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#include <linux/pm.h>
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#include "mali_kernel_linux.h"
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#ifdef CONFIG_PM_RUNTIME
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#include <linux/pm_runtime.h>
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#endif
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#include <asm/io.h>
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#include <linux/mali/mali_utgard.h>
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#include "mali_kernel_common.h"
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#include <linux/dma-mapping.h>
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#include <linux/moduleparam.h>
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#include "arm_core_scaling.h"
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#include "mali_executor.h"
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#if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
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#include <linux/devfreq_cooling.h>
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#include <linux/thermal.h>
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#endif
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static int mali_core_scaling_enable = 0;
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void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
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static u32 mali_read_phys(u32 phys_addr);
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#if defined(CONFIG_ARCH_REALVIEW)
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static void mali_write_phys(u32 phys_addr, u32 value);
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#endif
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#if defined(CONFIG_ARCH_VEXPRESS) && defined(CONFIG_ARM64)
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#define SECURE_MODE_CONTROL_HANDLER 0x6F02006C
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void *secure_mode_mapped_addr = NULL;
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/**
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* Reset GPU and enable/disable Mali secure mode.
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* @Return value:
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* 0: success
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* non-0: failure.
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*/
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static int mali_gpu_reset_and_secure_mode_enable_juno(void)
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{
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u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF;
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MALI_DEBUG_ASSERT(NULL != secure_mode_mapped_addr);
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iowrite32(1, ((u8 *)secure_mode_mapped_addr) + phys_offset);
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if (1 == (u32)ioread32(((u8 *)secure_mode_mapped_addr) + phys_offset)) {
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MALI_DEBUG_PRINT(3, ("Mali reset GPU and enable secured mode successfully! \n"));
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return 0;
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}
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MALI_PRINT_ERROR(("Failed to reset GPU and enable Mali secured mode !!! \n"));
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return -1;
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}
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static int mali_gpu_reset_and_secure_mode_disable_juno(void)
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{
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u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF;
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MALI_DEBUG_ASSERT(NULL != secure_mode_mapped_addr);
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iowrite32(0, ((u8 *)secure_mode_mapped_addr) + phys_offset);
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if (0 == (u32)ioread32(((u8 *)secure_mode_mapped_addr) + phys_offset)) {
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MALI_DEBUG_PRINT(3, ("Mali reset GPU and disable secured mode successfully! \n"));
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return 0;
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}
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MALI_PRINT_ERROR(("Failed to reset GPU and disable mali secured mode !!! \n"));
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return -1;
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}
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static int mali_secure_mode_init_juno(void)
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{
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u32 phys_addr_page = SECURE_MODE_CONTROL_HANDLER & 0xFFFFE000;
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u32 phys_offset = SECURE_MODE_CONTROL_HANDLER & 0x00001FFF;
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u32 map_size = phys_offset + sizeof(u32);
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MALI_DEBUG_ASSERT(NULL == secure_mode_mapped_addr);
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secure_mode_mapped_addr = ioremap(phys_addr_page, map_size);
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if (NULL != secure_mode_mapped_addr) {
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return mali_gpu_reset_and_secure_mode_disable_juno();
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}
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MALI_DEBUG_PRINT(2, ("Failed to ioremap for Mali secured mode! \n"));
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return -1;
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}
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static void mali_secure_mode_deinit_juno(void)
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{
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if (NULL != secure_mode_mapped_addr) {
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mali_gpu_reset_and_secure_mode_disable_juno();
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iounmap(secure_mode_mapped_addr);
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secure_mode_mapped_addr = NULL;
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}
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}
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#endif
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#ifndef CONFIG_MALI_DT
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static void mali_platform_device_release(struct device *device);
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#if defined(CONFIG_ARCH_VEXPRESS)
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#if defined(CONFIG_ARM64)
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/* Juno + Mali-450 MP6 in V7 FPGA */
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static struct resource mali_gpu_resources_m450_mp6[] = {
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MALI_GPU_RESOURCES_MALI450_MP6_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200)
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};
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static struct resource mali_gpu_resources_m470_mp4[] = {
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MALI_GPU_RESOURCES_MALI470_MP4_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200, 200)
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};
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static struct resource mali_gpu_resources_m470_mp3[] = {
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MALI_GPU_RESOURCES_MALI470_MP3_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200, 200, 200)
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};
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static struct resource mali_gpu_resources_m470_mp2[] = {
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MALI_GPU_RESOURCES_MALI470_MP2_PMU(0x6F040000, 200, 200, 200, 200, 200, 200, 200)
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};
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static struct resource mali_gpu_resources_m470_mp1[] = {
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MALI_GPU_RESOURCES_MALI470_MP1_PMU(0x6F040000, 200, 200, 200, 200, 200)
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};
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#else
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static struct resource mali_gpu_resources_m450_mp8[] = {
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MALI_GPU_RESOURCES_MALI450_MP8_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
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};
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static struct resource mali_gpu_resources_m450_mp6[] = {
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MALI_GPU_RESOURCES_MALI450_MP6_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
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};
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static struct resource mali_gpu_resources_m450_mp4[] = {
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MALI_GPU_RESOURCES_MALI450_MP4_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
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};
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static struct resource mali_gpu_resources_m470_mp4[] = {
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MALI_GPU_RESOURCES_MALI470_MP4_PMU(0xFC040000, -1, 70, 70, 70, 70, 70, 70, 70, 70, 70, 68)
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};
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#endif /* CONFIG_ARM64 */
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#elif defined(CONFIG_ARCH_REALVIEW)
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static struct resource mali_gpu_resources_m300[] = {
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MALI_GPU_RESOURCES_MALI300_PMU(0xC0000000, -1, -1, -1, -1)
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};
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static struct resource mali_gpu_resources_m400_mp1[] = {
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MALI_GPU_RESOURCES_MALI400_MP1_PMU(0xC0000000, -1, -1, -1, -1)
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};
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static struct resource mali_gpu_resources_m400_mp2[] = {
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MALI_GPU_RESOURCES_MALI400_MP2_PMU(0xC0000000, -1, -1, -1, -1, -1, -1)
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};
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#endif
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#endif
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#if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
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#define FALLBACK_STATIC_TEMPERATURE 55000
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static struct thermal_zone_device *gpu_tz;
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/* Calculate gpu static power example for reference */
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static unsigned long arm_model_static_power(struct devfreq *devfreq,
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unsigned long voltage)
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{
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int temperature, temp;
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int temp_squared, temp_cubed, temp_scaling_factor;
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const unsigned long coefficient = (410UL << 20) / (729000000UL >> 10);
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const unsigned long voltage_cubed = (voltage * voltage * voltage) >> 10;
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unsigned long static_power;
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if (gpu_tz) {
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int ret;
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ret = gpu_tz->ops->get_temp(gpu_tz, &temperature);
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if (ret) {
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MALI_DEBUG_PRINT(2, ("Error reading temperature for gpu thermal zone: %d\n", ret));
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temperature = FALLBACK_STATIC_TEMPERATURE;
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}
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} else {
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temperature = FALLBACK_STATIC_TEMPERATURE;
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}
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/* Calculate the temperature scaling factor. To be applied to the
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* voltage scaled power.
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*/
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temp = temperature / 1000;
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temp_squared = temp * temp;
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temp_cubed = temp_squared * temp;
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temp_scaling_factor =
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(2 * temp_cubed)
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- (80 * temp_squared)
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+ (4700 * temp)
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+ 32000;
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static_power = (((coefficient * voltage_cubed) >> 20)
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* temp_scaling_factor)
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/ 1000000;
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return static_power;
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}
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/* Calculate gpu dynamic power example for reference */
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static unsigned long arm_model_dynamic_power(struct devfreq *devfreq,
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unsigned long freq,
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unsigned long voltage)
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{
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/* The inputs: freq (f) is in Hz, and voltage (v) in mV.
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* The coefficient (c) is in mW/(MHz mV mV).
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*
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* This function calculates the dynamic power after this formula:
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* Pdyn (mW) = c (mW/(MHz*mV*mV)) * v (mV) * v (mV) * f (MHz)
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*/
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const unsigned long v2 = (voltage * voltage) / 1000; /* m*(V*V) */
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const unsigned long f_mhz = freq / 1000000; /* MHz */
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const unsigned long coefficient = 3600; /* mW/(MHz*mV*mV) */
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unsigned long dynamic_power;
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dynamic_power = (coefficient * v2 * f_mhz) / 1000000; /* mW */
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return dynamic_power;
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}
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struct devfreq_cooling_power arm_cooling_ops = {
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.get_static_power = arm_model_static_power,
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.get_dynamic_power = arm_model_dynamic_power,
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};
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#endif
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static struct mali_gpu_device_data mali_gpu_data = {
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#ifndef CONFIG_MALI_DT
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.pmu_switch_delay = 0xFF, /* do not have to be this high on FPGA, but it is good for testing to have a delay */
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#if defined(CONFIG_ARCH_VEXPRESS)
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.shared_mem_size = 256 * 1024 * 1024, /* 256MB */
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#endif
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#endif
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.max_job_runtime = 60000, /* 60 seconds */
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#if defined(CONFIG_ARCH_REALVIEW)
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.dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
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.dedicated_mem_size = 0x10000000, /* 256MB */
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#endif
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#if defined(CONFIG_ARM64)
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/* Some framebuffer drivers get the framebuffer dynamically, such as through GEM,
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* in which the memory resource can't be predicted in advance.
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*/
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.fb_start = 0x0,
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.fb_size = 0xFFFFF000,
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#else
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.fb_start = 0xe0000000,
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.fb_size = 0x01000000,
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#endif
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.control_interval = 1000, /* 1000ms */
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.utilization_callback = mali_gpu_utilization_callback,
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.get_clock_info = NULL,
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.get_freq = NULL,
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.set_freq = NULL,
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#if defined(CONFIG_ARCH_VEXPRESS) && defined(CONFIG_ARM64)
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.secure_mode_init = mali_secure_mode_init_juno,
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.secure_mode_deinit = mali_secure_mode_deinit_juno,
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.gpu_reset_and_secure_mode_enable = mali_gpu_reset_and_secure_mode_enable_juno,
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.gpu_reset_and_secure_mode_disable = mali_gpu_reset_and_secure_mode_disable_juno,
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#else
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.secure_mode_init = NULL,
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.secure_mode_deinit = NULL,
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.gpu_reset_and_secure_mode_enable = NULL,
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.gpu_reset_and_secure_mode_disable = NULL,
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#endif
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#if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
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.gpu_cooling_ops = &arm_cooling_ops,
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#endif
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};
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#ifndef CONFIG_MALI_DT
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static struct platform_device mali_gpu_device = {
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.name = MALI_GPU_NAME_UTGARD,
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.id = 0,
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.dev.release = mali_platform_device_release,
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.dev.dma_mask = &mali_gpu_device.dev.coherent_dma_mask,
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.dev.coherent_dma_mask = DMA_BIT_MASK(32),
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.dev.platform_data = &mali_gpu_data,
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};
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int mali_platform_device_register(void)
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{
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int err = -1;
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int num_pp_cores = 0;
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#if defined(CONFIG_ARCH_REALVIEW)
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u32 m400_gp_version;
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#endif
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MALI_DEBUG_PRINT(4, ("mali_platform_device_register() called\n"));
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/* Detect present Mali GPU and connect the correct resources to the device */
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#if defined(CONFIG_ARCH_VEXPRESS)
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#if defined(CONFIG_ARM64)
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)
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mali_gpu_device.dev.archdata.dma_ops = &dummy_dma_ops;
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#else
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mali_gpu_device.dev.archdata.dma_ops = dma_ops;
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#endif
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if ((mali_read_phys(0x6F000000) & 0x00600450) == 0x00600450) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP6 device\n"));
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num_pp_cores = 6;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp6);
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mali_gpu_device.resource = mali_gpu_resources_m450_mp6;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00400430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
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num_pp_cores = 4;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp4);
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mali_gpu_device.resource = mali_gpu_resources_m470_mp4;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00300430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP3 device\n"));
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num_pp_cores = 3;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp3);
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mali_gpu_device.resource = mali_gpu_resources_m470_mp3;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00200430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP2 device\n"));
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num_pp_cores = 2;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp2);
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mali_gpu_device.resource = mali_gpu_resources_m470_mp2;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00100430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP1 device\n"));
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num_pp_cores = 1;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp1);
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mali_gpu_device.resource = mali_gpu_resources_m470_mp1;
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}
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#else
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if (mali_read_phys(0xFC000000) == 0x00000450) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP8 device\n"));
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num_pp_cores = 8;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp8);
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mali_gpu_device.resource = mali_gpu_resources_m450_mp8;
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} else if (mali_read_phys(0xFC000000) == 0x40600450) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP6 device\n"));
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num_pp_cores = 6;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp6);
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mali_gpu_device.resource = mali_gpu_resources_m450_mp6;
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} else if (mali_read_phys(0xFC000000) == 0x40400450) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP4 device\n"));
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num_pp_cores = 4;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m450_mp4);
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mali_gpu_device.resource = mali_gpu_resources_m450_mp4;
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} else if (mali_read_phys(0xFC000000) == 0xFFFFFFFF) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
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num_pp_cores = 4;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m470_mp4);
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mali_gpu_device.resource = mali_gpu_resources_m470_mp4;
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}
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#endif /* CONFIG_ARM64 */
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#elif defined(CONFIG_ARCH_REALVIEW)
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m400_gp_version = mali_read_phys(0xC000006C);
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if ((m400_gp_version & 0xFFFF0000) == 0x0C070000) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-300 device\n"));
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num_pp_cores = 1;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m300);
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mali_gpu_device.resource = mali_gpu_resources_m300;
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mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
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} else if ((m400_gp_version & 0xFFFF0000) == 0x0B070000) {
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u32 fpga_fw_version = mali_read_phys(0xC0010000);
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if (fpga_fw_version == 0x130C008F || fpga_fw_version == 0x110C008F) {
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/* Mali-400 MP1 r1p0 or r1p1 */
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MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP1 device\n"));
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num_pp_cores = 1;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m400_mp1);
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mali_gpu_device.resource = mali_gpu_resources_m400_mp1;
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mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
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} else if (fpga_fw_version == 0x130C000F) {
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/* Mali-400 MP2 r1p1 */
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MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP2 device\n"));
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num_pp_cores = 2;
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mali_gpu_device.num_resources = ARRAY_SIZE(mali_gpu_resources_m400_mp2);
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mali_gpu_device.resource = mali_gpu_resources_m400_mp2;
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mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
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}
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}
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#endif
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/* Register the platform device */
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err = platform_device_register(&mali_gpu_device);
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if (0 == err) {
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#ifdef CONFIG_PM_RUNTIME
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
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pm_runtime_set_autosuspend_delay(&(mali_gpu_device.dev), 1000);
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pm_runtime_use_autosuspend(&(mali_gpu_device.dev));
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#endif
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pm_runtime_enable(&(mali_gpu_device.dev));
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#endif
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MALI_DEBUG_ASSERT(0 < num_pp_cores);
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mali_core_scaling_init(num_pp_cores);
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return 0;
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}
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return err;
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}
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void mali_platform_device_unregister(void)
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{
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MALI_DEBUG_PRINT(4, ("mali_platform_device_unregister() called\n"));
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mali_core_scaling_term();
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#ifdef CONFIG_PM_RUNTIME
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pm_runtime_disable(&(mali_gpu_device.dev));
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#endif
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platform_device_unregister(&mali_gpu_device);
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platform_device_put(&mali_gpu_device);
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#if defined(CONFIG_ARCH_REALVIEW)
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mali_write_phys(0xC0010020, 0x9); /* Restore default (legacy) memory mapping */
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#endif
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}
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static void mali_platform_device_release(struct device *device)
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{
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MALI_DEBUG_PRINT(4, ("mali_platform_device_release() called\n"));
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}
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#else /* CONFIG_MALI_DT */
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int mali_platform_device_init(struct platform_device *device)
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{
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int num_pp_cores = 0;
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int err = -1;
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#if defined(CONFIG_ARCH_REALVIEW)
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u32 m400_gp_version;
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#endif
|
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/* Detect present Mali GPU and connect the correct resources to the device */
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#if defined(CONFIG_ARCH_VEXPRESS)
|
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#if defined(CONFIG_ARM64)
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if ((mali_read_phys(0x6F000000) & 0x00600450) == 0x00600450) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP6 device\n"));
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num_pp_cores = 6;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00400430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
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num_pp_cores = 4;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00300430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP3 device\n"));
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num_pp_cores = 3;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00200430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP2 device\n"));
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num_pp_cores = 2;
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} else if ((mali_read_phys(0x6F000000) & 0x00F00430) == 0x00100430) {
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MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP1 device\n"));
|
num_pp_cores = 1;
|
}
|
#else
|
if (mali_read_phys(0xFC000000) == 0x00000450) {
|
MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP8 device\n"));
|
num_pp_cores = 8;
|
} else if (mali_read_phys(0xFC000000) == 0x40400450) {
|
MALI_DEBUG_PRINT(4, ("Registering Mali-450 MP4 device\n"));
|
num_pp_cores = 4;
|
} else if (mali_read_phys(0xFC000000) == 0xFFFFFFFF) {
|
MALI_DEBUG_PRINT(4, ("Registering Mali-470 MP4 device\n"));
|
num_pp_cores = 4;
|
}
|
#endif
|
|
#elif defined(CONFIG_ARCH_REALVIEW)
|
|
m400_gp_version = mali_read_phys(0xC000006C);
|
if ((m400_gp_version & 0xFFFF0000) == 0x0C070000) {
|
MALI_DEBUG_PRINT(4, ("Registering Mali-300 device\n"));
|
num_pp_cores = 1;
|
mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
|
} else if ((m400_gp_version & 0xFFFF0000) == 0x0B070000) {
|
u32 fpga_fw_version = mali_read_phys(0xC0010000);
|
if (fpga_fw_version == 0x130C008F || fpga_fw_version == 0x110C008F) {
|
/* Mali-400 MP1 r1p0 or r1p1 */
|
MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP1 device\n"));
|
num_pp_cores = 1;
|
mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
|
} else if (fpga_fw_version == 0x130C000F) {
|
/* Mali-400 MP2 r1p1 */
|
MALI_DEBUG_PRINT(4, ("Registering Mali-400 MP2 device\n"));
|
num_pp_cores = 2;
|
mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
|
}
|
}
|
#endif
|
|
/* After kernel 3.15 device tree will default set dev
|
* related parameters in of_platform_device_create_pdata.
|
* But kernel changes from version to version,
|
* For example 3.10 didn't include device->dev.dma_mask parameter setting,
|
* if we didn't include here will cause dma_mapping error,
|
* but in kernel 3.15 it include device->dev.dma_mask parameter setting,
|
* so it's better to set must need paramter by DDK itself.
|
*/
|
if (!device->dev.dma_mask)
|
device->dev.dma_mask = &device->dev.coherent_dma_mask;
|
device->dev.archdata.dma_ops = dma_ops;
|
|
err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
|
|
if (0 == err) {
|
#ifdef CONFIG_PM_RUNTIME
|
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
|
pm_runtime_set_autosuspend_delay(&(device->dev), 1000);
|
pm_runtime_use_autosuspend(&(device->dev));
|
#endif
|
pm_runtime_enable(&(device->dev));
|
#endif
|
MALI_DEBUG_ASSERT(0 < num_pp_cores);
|
mali_core_scaling_init(num_pp_cores);
|
}
|
|
#if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL)
|
/* Some Socs didn't support the devfreq thermal for mali */
|
if (of_machine_is_compatible("rockchip,rk3036"))
|
return 0;
|
|
/* Get thermal zone */
|
gpu_tz = thermal_zone_get_zone_by_name("soc_thermal");
|
if (IS_ERR(gpu_tz)) {
|
MALI_DEBUG_PRINT(2, ("Error getting gpu thermal zone (%ld), not yet ready?\n",
|
PTR_ERR(gpu_tz)));
|
gpu_tz = NULL;
|
|
err = -EPROBE_DEFER;
|
}
|
#endif
|
|
return err;
|
}
|
|
int mali_platform_device_deinit(struct platform_device *device)
|
{
|
MALI_IGNORE(device);
|
|
MALI_DEBUG_PRINT(4, ("mali_platform_device_deinit() called\n"));
|
|
mali_core_scaling_term();
|
#ifdef CONFIG_PM_RUNTIME
|
pm_runtime_disable(&(device->dev));
|
#endif
|
|
#if defined(CONFIG_ARCH_REALVIEW)
|
mali_write_phys(0xC0010020, 0x9); /* Restore default (legacy) memory mapping */
|
#endif
|
|
return 0;
|
}
|
|
#endif /* CONFIG_MALI_DT */
|
|
static u32 mali_read_phys(u32 phys_addr)
|
{
|
u32 phys_addr_page = phys_addr & 0xFFFFE000;
|
u32 phys_offset = phys_addr & 0x00001FFF;
|
u32 map_size = phys_offset + sizeof(u32);
|
u32 ret = 0xDEADBEEF;
|
void *mem_mapped = ioremap(phys_addr_page, map_size);
|
if (NULL != mem_mapped) {
|
ret = (u32)ioread32(((u8 *)mem_mapped) + phys_offset);
|
iounmap(mem_mapped);
|
}
|
|
return ret;
|
}
|
|
#if defined(CONFIG_ARCH_REALVIEW)
|
static void mali_write_phys(u32 phys_addr, u32 value)
|
{
|
u32 phys_addr_page = phys_addr & 0xFFFFE000;
|
u32 phys_offset = phys_addr & 0x00001FFF;
|
u32 map_size = phys_offset + sizeof(u32);
|
void *mem_mapped = ioremap(phys_addr_page, map_size);
|
if (NULL != mem_mapped) {
|
iowrite32(value, ((u8 *)mem_mapped) + phys_offset);
|
iounmap(mem_mapped);
|
}
|
}
|
#endif
|
|
static int param_set_core_scaling(const char *val, const struct kernel_param *kp)
|
{
|
int ret = param_set_int(val, kp);
|
|
if (1 == mali_core_scaling_enable) {
|
mali_core_scaling_sync(mali_executor_get_num_cores_enabled());
|
}
|
return ret;
|
}
|
|
static struct kernel_param_ops param_ops_core_scaling = {
|
.set = param_set_core_scaling,
|
.get = param_get_int,
|
};
|
|
module_param_cb(mali_core_scaling_enable, ¶m_ops_core_scaling, &mali_core_scaling_enable, 0644);
|
MODULE_PARM_DESC(mali_core_scaling_enable, "1 means to enable core scaling policy, 0 means to disable core scaling policy");
|
|
void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
|
{
|
if (1 == mali_core_scaling_enable) {
|
mali_core_scaling_update(data);
|
}
|
}
|
