/*
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* Copyright (C) 2010-2017 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
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*
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* A copy of the licence is included with the program, and can also be obtained from Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "mali_kernel_common.h"
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#include "mali_osk.h"
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#include "mali_l2_cache.h"
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#include "mali_hw_core.h"
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#include "mali_scheduler.h"
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#include "mali_pm.h"
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#include "mali_pm_domain.h"
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/**
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* Size of the Mali L2 cache registers in bytes
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*/
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#define MALI400_L2_CACHE_REGISTERS_SIZE 0x30
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/**
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* Mali L2 cache register numbers
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* Used in the register read/write routines.
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* See the hardware documentation for more information about each register
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*/
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typedef enum mali_l2_cache_register {
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MALI400_L2_CACHE_REGISTER_SIZE = 0x0004,
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MALI400_L2_CACHE_REGISTER_STATUS = 0x0008,
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/*unused = 0x000C */
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MALI400_L2_CACHE_REGISTER_COMMAND = 0x0010,
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MALI400_L2_CACHE_REGISTER_CLEAR_PAGE = 0x0014,
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MALI400_L2_CACHE_REGISTER_MAX_READS = 0x0018,
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MALI400_L2_CACHE_REGISTER_ENABLE = 0x001C,
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MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0 = 0x0020,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0 = 0x0024,
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MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1 = 0x0028,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1 = 0x002C,
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} mali_l2_cache_register;
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/**
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* Mali L2 cache commands
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* These are the commands that can be sent to the Mali L2 cache unit
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*/
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typedef enum mali_l2_cache_command {
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MALI400_L2_CACHE_COMMAND_CLEAR_ALL = 0x01,
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} mali_l2_cache_command;
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/**
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* Mali L2 cache commands
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* These are the commands that can be sent to the Mali L2 cache unit
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*/
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typedef enum mali_l2_cache_enable {
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MALI400_L2_CACHE_ENABLE_DEFAULT = 0x0, /* Default */
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MALI400_L2_CACHE_ENABLE_ACCESS = 0x01,
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MALI400_L2_CACHE_ENABLE_READ_ALLOCATE = 0x02,
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} mali_l2_cache_enable;
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/**
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* Mali L2 cache status bits
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*/
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typedef enum mali_l2_cache_status {
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MALI400_L2_CACHE_STATUS_COMMAND_BUSY = 0x01,
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MALI400_L2_CACHE_STATUS_DATA_BUSY = 0x02,
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} mali_l2_cache_status;
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#define MALI400_L2_MAX_READS_NOT_SET -1
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static struct mali_l2_cache_core *
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mali_global_l2s[MALI_MAX_NUMBER_OF_L2_CACHE_CORES] = { NULL, };
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static u32 mali_global_num_l2s = 0;
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int mali_l2_max_reads = MALI400_L2_MAX_READS_NOT_SET;
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/* Local helper functions */
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static void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
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static _mali_osk_errcode_t mali_l2_cache_send_command(
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struct mali_l2_cache_core *cache, u32 reg, u32 val);
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static void mali_l2_cache_lock(struct mali_l2_cache_core *cache)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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_mali_osk_spinlock_irq_lock(cache->lock);
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}
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static void mali_l2_cache_unlock(struct mali_l2_cache_core *cache)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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_mali_osk_spinlock_irq_unlock(cache->lock);
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}
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/* Implementation of the L2 cache interface */
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struct mali_l2_cache_core *mali_l2_cache_create(
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_mali_osk_resource_t *resource, u32 domain_index)
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{
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struct mali_l2_cache_core *cache = NULL;
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#if defined(DEBUG)
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u32 cache_size;
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#endif
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MALI_DEBUG_PRINT(4, ("Mali L2 cache: Creating Mali L2 cache: %s\n",
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resource->description));
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if (mali_global_num_l2s >= MALI_MAX_NUMBER_OF_L2_CACHE_CORES) {
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MALI_PRINT_ERROR(("Mali L2 cache: Too many L2 caches\n"));
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return NULL;
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}
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cache = _mali_osk_malloc(sizeof(struct mali_l2_cache_core));
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if (NULL == cache) {
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MALI_PRINT_ERROR(("Mali L2 cache: Failed to allocate memory for L2 cache core\n"));
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return NULL;
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}
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cache->core_id = mali_global_num_l2s;
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cache->counter_src0 = MALI_HW_CORE_NO_COUNTER;
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cache->counter_src1 = MALI_HW_CORE_NO_COUNTER;
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cache->counter_value0_base = 0;
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cache->counter_value1_base = 0;
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cache->pm_domain = NULL;
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cache->power_is_on = MALI_FALSE;
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cache->last_invalidated_id = 0;
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if (_MALI_OSK_ERR_OK != mali_hw_core_create(&cache->hw_core,
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resource, MALI400_L2_CACHE_REGISTERS_SIZE)) {
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_mali_osk_free(cache);
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return NULL;
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}
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#if defined(DEBUG)
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cache_size = mali_hw_core_register_read(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_SIZE);
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MALI_DEBUG_PRINT(2, ("Mali L2 cache: Created %s: % 3uK, %u-way, % 2ubyte cache line, % 3ubit external bus\n",
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resource->description,
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1 << (((cache_size >> 16) & 0xff) - 10),
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1 << ((cache_size >> 8) & 0xff),
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1 << (cache_size & 0xff),
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1 << ((cache_size >> 24) & 0xff)));
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#endif
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cache->lock = _mali_osk_spinlock_irq_init(_MALI_OSK_LOCKFLAG_ORDERED,
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_MALI_OSK_LOCK_ORDER_L2);
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if (NULL == cache->lock) {
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MALI_PRINT_ERROR(("Mali L2 cache: Failed to create counter lock for L2 cache core %s\n",
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cache->hw_core.description));
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mali_hw_core_delete(&cache->hw_core);
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_mali_osk_free(cache);
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return NULL;
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}
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/* register with correct power domain */
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cache->pm_domain = mali_pm_register_l2_cache(
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domain_index, cache);
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mali_global_l2s[mali_global_num_l2s] = cache;
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mali_global_num_l2s++;
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return cache;
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}
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void mali_l2_cache_delete(struct mali_l2_cache_core *cache)
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{
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u32 i;
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for (i = 0; i < mali_global_num_l2s; i++) {
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if (mali_global_l2s[i] != cache) {
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continue;
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}
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mali_global_l2s[i] = NULL;
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mali_global_num_l2s--;
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if (i == mali_global_num_l2s) {
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/* Removed last element, nothing more to do */
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break;
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}
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/*
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* We removed a l2 cache from the middle of the array,
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* so move the last l2 cache to current position
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*/
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mali_global_l2s[i] = mali_global_l2s[mali_global_num_l2s];
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mali_global_l2s[mali_global_num_l2s] = NULL;
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/* All good */
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break;
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}
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_mali_osk_spinlock_irq_term(cache->lock);
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mali_hw_core_delete(&cache->hw_core);
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_mali_osk_free(cache);
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}
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void mali_l2_cache_power_up(struct mali_l2_cache_core *cache)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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mali_l2_cache_lock(cache);
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mali_l2_cache_reset(cache);
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if ((1 << MALI_DOMAIN_INDEX_DUMMY) != cache->pm_domain->pmu_mask)
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MALI_DEBUG_ASSERT(MALI_FALSE == cache->power_is_on);
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cache->power_is_on = MALI_TRUE;
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mali_l2_cache_unlock(cache);
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}
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void mali_l2_cache_power_down(struct mali_l2_cache_core *cache)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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mali_l2_cache_lock(cache);
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MALI_DEBUG_ASSERT(MALI_TRUE == cache->power_is_on);
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/*
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* The HW counters will start from zero again when we resume,
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* but we should report counters as always increasing.
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* Take a copy of the HW values now in order to add this to
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* the values we report after being powered up.
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*
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* The physical power off of the L2 cache might be outside our
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* own control (e.g. runtime PM). That is why we must manually
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* set set the counter value to zero as well.
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*/
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if (cache->counter_src0 != MALI_HW_CORE_NO_COUNTER) {
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cache->counter_value0_base += mali_hw_core_register_read(
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&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0);
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mali_hw_core_register_write(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0, 0);
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}
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if (cache->counter_src1 != MALI_HW_CORE_NO_COUNTER) {
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cache->counter_value1_base += mali_hw_core_register_read(
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&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1);
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mali_hw_core_register_write(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1, 0);
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}
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cache->power_is_on = MALI_FALSE;
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mali_l2_cache_unlock(cache);
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}
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void mali_l2_cache_core_set_counter_src(
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struct mali_l2_cache_core *cache, u32 source_id, u32 counter)
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{
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u32 reg_offset_src;
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u32 reg_offset_val;
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MALI_DEBUG_ASSERT_POINTER(cache);
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MALI_DEBUG_ASSERT(source_id >= 0 && source_id <= 1);
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mali_l2_cache_lock(cache);
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if (0 == source_id) {
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/* start counting from 0 */
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cache->counter_value0_base = 0;
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cache->counter_src0 = counter;
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reg_offset_src = MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0;
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reg_offset_val = MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0;
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} else {
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/* start counting from 0 */
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cache->counter_value1_base = 0;
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cache->counter_src1 = counter;
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reg_offset_src = MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1;
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reg_offset_val = MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1;
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}
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if (cache->power_is_on) {
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u32 hw_src;
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if (MALI_HW_CORE_NO_COUNTER != counter) {
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hw_src = counter;
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} else {
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hw_src = 0; /* disable value for HW */
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}
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/* Set counter src */
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mali_hw_core_register_write(&cache->hw_core,
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reg_offset_src, hw_src);
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/* Make sure the HW starts counting from 0 again */
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mali_hw_core_register_write(&cache->hw_core,
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reg_offset_val, 0);
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}
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mali_l2_cache_unlock(cache);
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}
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void mali_l2_cache_core_get_counter_values(
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struct mali_l2_cache_core *cache,
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u32 *src0, u32 *value0, u32 *src1, u32 *value1)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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MALI_DEBUG_ASSERT(NULL != src0);
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MALI_DEBUG_ASSERT(NULL != value0);
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MALI_DEBUG_ASSERT(NULL != src1);
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MALI_DEBUG_ASSERT(NULL != value1);
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mali_l2_cache_lock(cache);
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*src0 = cache->counter_src0;
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*src1 = cache->counter_src1;
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if (cache->counter_src0 != MALI_HW_CORE_NO_COUNTER) {
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if (MALI_TRUE == cache->power_is_on) {
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*value0 = mali_hw_core_register_read(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0);
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} else {
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*value0 = 0;
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}
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/* Add base offset value (in case we have been power off) */
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*value0 += cache->counter_value0_base;
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}
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if (cache->counter_src1 != MALI_HW_CORE_NO_COUNTER) {
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if (MALI_TRUE == cache->power_is_on) {
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*value1 = mali_hw_core_register_read(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1);
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} else {
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*value1 = 0;
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}
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/* Add base offset value (in case we have been power off) */
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*value1 += cache->counter_value1_base;
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}
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mali_l2_cache_unlock(cache);
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}
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struct mali_l2_cache_core *mali_l2_cache_core_get_glob_l2_core(u32 index)
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{
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if (mali_global_num_l2s > index) {
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return mali_global_l2s[index];
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}
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return NULL;
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}
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u32 mali_l2_cache_core_get_glob_num_l2_cores(void)
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{
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return mali_global_num_l2s;
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}
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void mali_l2_cache_invalidate(struct mali_l2_cache_core *cache)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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if (NULL == cache) {
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return;
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}
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mali_l2_cache_lock(cache);
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cache->last_invalidated_id = mali_scheduler_get_new_cache_order();
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mali_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_COMMAND,
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MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
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mali_l2_cache_unlock(cache);
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}
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void mali_l2_cache_invalidate_conditional(
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struct mali_l2_cache_core *cache, u32 id)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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if (NULL == cache) {
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return;
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}
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/*
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* If the last cache invalidation was done by a job with a higher id we
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* don't have to flush. Since user space will store jobs w/ their
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* corresponding memory in sequence (first job #0, then job #1, ...),
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* we don't have to flush for job n-1 if job n has already invalidated
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* the cache since we know for sure that job n-1's memory was already
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* written when job n was started.
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*/
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mali_l2_cache_lock(cache);
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if (((s32)id) > ((s32)cache->last_invalidated_id)) {
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/* Set latest invalidated id to current "point in time" */
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cache->last_invalidated_id =
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mali_scheduler_get_new_cache_order();
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mali_l2_cache_send_command(cache,
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MALI400_L2_CACHE_REGISTER_COMMAND,
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MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
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}
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mali_l2_cache_unlock(cache);
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}
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void mali_l2_cache_invalidate_all(void)
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{
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u32 i;
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for (i = 0; i < mali_global_num_l2s; i++) {
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struct mali_l2_cache_core *cache = mali_global_l2s[i];
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_mali_osk_errcode_t ret;
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MALI_DEBUG_ASSERT_POINTER(cache);
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mali_l2_cache_lock(cache);
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if (MALI_TRUE != cache->power_is_on) {
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mali_l2_cache_unlock(cache);
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continue;
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}
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cache->last_invalidated_id =
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mali_scheduler_get_new_cache_order();
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ret = mali_l2_cache_send_command(cache,
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MALI400_L2_CACHE_REGISTER_COMMAND,
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MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
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if (_MALI_OSK_ERR_OK != ret) {
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MALI_PRINT_ERROR(("Failed to invalidate cache\n"));
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}
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mali_l2_cache_unlock(cache);
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}
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}
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void mali_l2_cache_invalidate_all_pages(u32 *pages, u32 num_pages)
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{
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u32 i;
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for (i = 0; i < mali_global_num_l2s; i++) {
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struct mali_l2_cache_core *cache = mali_global_l2s[i];
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u32 j;
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MALI_DEBUG_ASSERT_POINTER(cache);
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mali_l2_cache_lock(cache);
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if (MALI_TRUE != cache->power_is_on) {
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mali_l2_cache_unlock(cache);
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continue;
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}
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for (j = 0; j < num_pages; j++) {
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_mali_osk_errcode_t ret;
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ret = mali_l2_cache_send_command(cache,
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MALI400_L2_CACHE_REGISTER_CLEAR_PAGE,
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pages[j]);
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if (_MALI_OSK_ERR_OK != ret) {
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MALI_PRINT_ERROR(("Failed to invalidate cache (page)\n"));
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}
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}
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mali_l2_cache_unlock(cache);
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}
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}
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/* -------- local helper functions below -------- */
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static void mali_l2_cache_reset(struct mali_l2_cache_core *cache)
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{
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MALI_DEBUG_ASSERT_POINTER(cache);
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MALI_DEBUG_ASSERT_LOCK_HELD(cache->lock);
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/* Invalidate cache (just to keep it in a known state at startup) */
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mali_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_COMMAND,
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MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
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/* Enable cache */
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mali_hw_core_register_write(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_ENABLE,
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(u32)MALI400_L2_CACHE_ENABLE_ACCESS |
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(u32)MALI400_L2_CACHE_ENABLE_READ_ALLOCATE);
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if (MALI400_L2_MAX_READS_NOT_SET != mali_l2_max_reads) {
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mali_hw_core_register_write(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_MAX_READS,
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(u32)mali_l2_max_reads);
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}
|
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/* Restart any performance counters (if enabled) */
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if (cache->counter_src0 != MALI_HW_CORE_NO_COUNTER) {
|
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mali_hw_core_register_write(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0,
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cache->counter_src0);
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}
|
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if (cache->counter_src1 != MALI_HW_CORE_NO_COUNTER) {
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mali_hw_core_register_write(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1,
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cache->counter_src1);
|
}
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}
|
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static _mali_osk_errcode_t mali_l2_cache_send_command(
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struct mali_l2_cache_core *cache, u32 reg, u32 val)
|
{
|
int i = 0;
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const int loop_count = 100000;
|
|
MALI_DEBUG_ASSERT_POINTER(cache);
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MALI_DEBUG_ASSERT_LOCK_HELD(cache->lock);
|
|
/*
|
* First, wait for L2 cache command handler to go idle.
|
* (Commands received while processing another command will be ignored)
|
*/
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for (i = 0; i < loop_count; i++) {
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if (!(mali_hw_core_register_read(&cache->hw_core,
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MALI400_L2_CACHE_REGISTER_STATUS) &
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(u32)MALI400_L2_CACHE_STATUS_COMMAND_BUSY)) {
|
break;
|
}
|
}
|
|
if (i == loop_count) {
|
MALI_DEBUG_PRINT(1, ("Mali L2 cache: aborting wait for command interface to go idle\n"));
|
return _MALI_OSK_ERR_FAULT;
|
}
|
|
/* then issue the command */
|
mali_hw_core_register_write(&cache->hw_core, reg, val);
|
|
return _MALI_OSK_ERR_OK;
|
}
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