/*
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* Rockchip VPU codec driver
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*
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* Copyright (C) 2014 Google, Inc.
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* Tomasz Figa <tfiga@chromium.org>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef ROCKCHIP_VPU_HW_H_
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#define ROCKCHIP_VPU_HW_H_
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#include <media/videobuf2-core.h>
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#define ROCKCHIP_HEADER_SIZE 1280
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#define ROCKCHIP_HW_PARAMS_SIZE 5487
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#define ROCKCHIP_RET_PARAMS_SIZE 488
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struct rockchip_vpu_dev;
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struct rockchip_vpu_ctx;
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struct rockchip_vpu_buf;
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/**
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* enum rockchip_vpu_enc_fmt - source format ID for hardware registers.
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*/
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enum rockchip_vpu_enc_fmt {
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ROCKCHIP_VPU_ENC_FMT_YUV420P = 0,
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ROCKCHIP_VPU_ENC_FMT_YUV420SP = 1,
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ROCKCHIP_VPU_ENC_FMT_YUYV422 = 2,
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ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3,
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};
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/**
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* struct rk3288_vp8e_reg_params - low level encoding parameters
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* TODO: Create abstract structures for more generic controls or just
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* remove unused fields.
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*/
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struct rk3288_vp8e_reg_params {
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u32 unused_00[5];
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u32 hdr_len;
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u32 unused_18[8];
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u32 enc_ctrl;
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u32 unused_3c;
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u32 enc_ctrl0;
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u32 enc_ctrl1;
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u32 enc_ctrl2;
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u32 enc_ctrl3;
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u32 enc_ctrl5;
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u32 enc_ctrl4;
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u32 str_hdr_rem_msb;
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u32 str_hdr_rem_lsb;
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u32 unused_60;
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u32 mad_ctrl;
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u32 unused_68;
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u32 qp_val[8];
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u32 bool_enc;
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u32 vp8_ctrl0;
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u32 rlc_ctrl;
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u32 mb_ctrl;
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u32 unused_9c[14];
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u32 rgb_yuv_coeff[2];
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u32 rgb_mask_msb;
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u32 intra_area_ctrl;
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u32 cir_intra_ctrl;
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u32 unused_e8[2];
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u32 first_roi_area;
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u32 second_roi_area;
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u32 mvc_ctrl;
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u32 unused_fc;
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u32 intra_penalty[7];
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u32 unused_11c;
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u32 seg_qp[24];
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u32 dmv_4p_1p_penalty[32];
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u32 dmv_qpel_penalty[32];
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u32 vp8_ctrl1;
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u32 bit_cost_golden;
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u32 loop_flt_delta[2];
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};
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/**
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* struct rk3288_h264e_reg_params - low level encoding parameters
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* TODO: Create abstract structures for more generic controls or just
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* remove unused fields.
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*/
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struct rk3288_h264e_reg_params {
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u32 frame_coding_type;
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s32 pic_init_qp;
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s32 slice_alpha_offset;
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s32 slice_beta_offset;
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s32 chroma_qp_index_offset;
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s32 filter_disable;
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u16 idr_pic_id;
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s32 pps_id;
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s32 frame_num;
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s32 slice_size_mb_rows;
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s32 h264_inter4x4_disabled;
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s32 enable_cabac;
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s32 transform8x8_mode;
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s32 cabac_init_idc;
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/* rate control relevant */
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s32 qp;
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s32 mad_qp_delta;
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s32 mad_threshold;
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s32 qp_min;
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s32 qp_max;
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s32 cp_distance_mbs;
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s32 cp_target[10];
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s32 target_error[7];
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s32 delta_qp[7];
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};
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/**
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* struct rockchip_reg_params - low level encoding parameters
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*/
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struct rockchip_reg_params {
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/* Mode-specific data. */
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union {
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const struct rk3288_h264e_reg_params rk3288_h264e;
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const struct rk3288_vp8e_reg_params rk3288_vp8e;
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};
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};
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struct rockchip_vpu_h264e_feedback {
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s32 qp_sum;
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s32 cp[10];
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s32 mad_count;
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s32 rlc_count;
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};
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/**
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* struct rockchip_vpu_aux_buf - auxiliary DMA buffer for hardware data
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* @cpu: CPU pointer to the buffer.
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* @dma: DMA address of the buffer.
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* @size: Size of the buffer.
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*/
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struct rockchip_vpu_aux_buf {
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void *cpu;
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dma_addr_t dma;
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size_t size;
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};
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/**
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* struct rockchip_vpu_vp8e_hw_ctx - Context private data specific to codec mode.
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* @ctrl_buf: VP8 control buffer.
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* @ext_buf: VP8 ext data buffer.
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* @mv_buf: VP8 motion vector buffer.
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* @ref_rec_ptr: Bit flag for swapping ref and rec buffers every frame.
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*/
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struct rockchip_vpu_vp8e_hw_ctx {
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struct rockchip_vpu_aux_buf ctrl_buf;
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struct rockchip_vpu_aux_buf ext_buf;
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struct rockchip_vpu_aux_buf mv_buf;
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u8 ref_rec_ptr:1;
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};
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/**
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* struct rockchip_vpu_vp8d_hw_ctx - Context private data of VP8 decoder.
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* @segment_map: Segment map buffer.
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* @prob_tbl: Probability table buffer.
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*/
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struct rockchip_vpu_vp8d_hw_ctx {
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struct rockchip_vpu_aux_buf segment_map;
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struct rockchip_vpu_aux_buf prob_tbl;
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};
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/**
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* struct rockchip_vpu_h264d_hw_ctx - Per context data specific to H264 decoding.
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* @priv_tbl: Private auxiliary buffer for hardware.
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*/
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struct rockchip_vpu_h264d_hw_ctx {
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struct rockchip_vpu_aux_buf priv_tbl;
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};
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/**
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* struct rockchip_vpu_h264e_hw_ctx - Context private data specific to codec mode.
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* @ctrl_buf: H264 control buffer.
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* @ext_buf: H264 ext data buffer.
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* @ref_rec_ptr: Bit flag for swapping ref and rec buffers every frame.
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*/
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struct rockchip_vpu_h264e_hw_ctx {
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struct rockchip_vpu_aux_buf cabac_tbl[3];
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struct rockchip_vpu_aux_buf ext_buf;
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u8 ref_rec_ptr:1;
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};
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/**
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* struct rockchip_vpu_hw_ctx - Context private data of hardware code.
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* @codec_ops: Set of operations associated with current codec mode.
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*/
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struct rockchip_vpu_hw_ctx {
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const struct rockchip_vpu_codec_ops *codec_ops;
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/* Specific for particular codec modes. */
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union {
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struct rockchip_vpu_vp8e_hw_ctx vp8e;
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struct rockchip_vpu_vp8d_hw_ctx vp8d;
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struct rockchip_vpu_h264e_hw_ctx h264e;
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struct rockchip_vpu_h264d_hw_ctx h264d;
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/* Other modes will need different data. */
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};
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};
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int rockchip_vpu_hw_probe(struct rockchip_vpu_dev *vpu);
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void rockchip_vpu_hw_remove(struct rockchip_vpu_dev *vpu);
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void rockchip_vpu_power_on(struct rockchip_vpu_dev *vpu);
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int rockchip_vpu_init(struct rockchip_vpu_ctx *ctx);
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void rockchip_vpu_deinit(struct rockchip_vpu_ctx *ctx);
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void rockchip_vpu_run(struct rockchip_vpu_ctx *ctx);
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/* Ops for rk3288 vpu */
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int rk3288_vpu_enc_irq(int irq, struct rockchip_vpu_dev *vpu);
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int rk3288_vpu_dec_irq(int irq, struct rockchip_vpu_dev *vpu);
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void rk3288_vpu_enc_reset(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_dec_reset(struct rockchip_vpu_ctx *ctx);
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/* Run ops for rk3288 H264 decoder */
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int rk3288_vpu_h264d_init(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_h264d_exit(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_h264d_run(struct rockchip_vpu_ctx *ctx);
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/* Run ops for rk3288 h264 encoder */
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int rk3288_vpu_h264e_init(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_h264e_exit(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_h264e_run(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_h264e_done(struct rockchip_vpu_ctx *ctx,
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enum vb2_buffer_state result);
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/* Run ops for rk3288 VP8 decoder */
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int rk3288_vpu_vp8d_init(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_vp8d_exit(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_vp8d_run(struct rockchip_vpu_ctx *ctx);
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/* Run ops for rk3288 VP8 encoder */
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int rk3288_vpu_vp8e_init(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_vp8e_exit(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_vp8e_run(struct rockchip_vpu_ctx *ctx);
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void rk3288_vpu_vp8e_done(struct rockchip_vpu_ctx *ctx,
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enum vb2_buffer_state result);
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const struct rockchip_reg_params *rk3288_vpu_vp8e_get_dummy_params(void);
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void rockchip_vpu_vp8e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
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struct rockchip_vpu_buf *dst_buf);
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void rockchip_vpu_h264e_assemble_bitstream(struct rockchip_vpu_ctx *ctx,
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struct rockchip_vpu_buf *dst_buf);
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#endif /* ROCKCHIP_VPU_HW_H_ */
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