/*
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* Rockchip VPU codec driver
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*
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* Copyright (C) 2014 Google, Inc.
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* Tomasz Figa <tfiga@chromium.org>
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*
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* Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
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*
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* Copyright (C) 2011 Samsung Electronics Co., Ltd.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef ROCKCHIP_VPU_COMMON_H_
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#define ROCKCHIP_VPU_COMMON_H_
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/* Enable debugging by default for now. */
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#define DEBUG
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#include <linux/platform_device.h>
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#include <linux/videodev2.h>
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#include <linux/wait.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ioctl.h>
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#include <media/videobuf2-core.h>
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#include <media/videobuf2-dma-contig.h>
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#include "rockchip_vpu_hw.h"
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#define ROCKCHIP_VPU_NAME "rockchip-vpu"
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#define ROCKCHIP_VPU_DEC_NAME "rockchip-vpu-dec"
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#define ROCKCHIP_VPU_ENC_NAME "rockchip-vpu-enc"
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#define V4L2_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0x1000)
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#define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
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#define ROCKCHIP_VPU_MAX_CTRLS 32
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#define MB_DIM 16
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#define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, MB_DIM)
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#define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, MB_DIM)
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struct rockchip_vpu_ctx;
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struct rockchip_vpu_codec_ops;
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/**
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* struct rockchip_vpu_variant - information about VPU hardware variant
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*
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* @hw_id: Top 16 bits (product ID) of hardware ID register.
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* @name: Vpu name.
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* @codecs: Supported codecs of this vpu.
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* @enc_offset: Offset from VPU base to encoder registers.
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* @enc_reg_num: Number of registers of encoder block.
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* @dec_offset: Offset from VPU base to decoder registers.
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* @dec_reg_num: Number of registers of decoder block.
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*/
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struct rockchip_vpu_variant {
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char *name;
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unsigned codecs;
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unsigned enc_offset;
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unsigned enc_reg_num;
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unsigned dec_offset;
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unsigned dec_reg_num;
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};
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/**
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* enum rockchip_vpu_codec_mode - codec operating mode.
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* @RK_VPU_CODEC_NONE: Used for RAW video formats.
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* @RK3288_VPU_CODEC_H264D: Rk3288 H264 decoder.
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* @RK3288_VPU_CODEC_H264E: Rk3288 H264 encoder.
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* @RK3288_VPU_CODEC_VP8D: Rk3288 VP8 decoder.
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* @RK3288_VPU_CODEC_VP8E: Rk3288 VP8 encoder.
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*/
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enum rockchip_vpu_codec_mode {
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RK_VPU_CODEC_NONE = (1 << 0),
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RK3288_VPU_CODEC_H264D = (1 << 1),
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RK3288_VPU_CODEC_H264E = (1 << 2),
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RK3288_VPU_CODEC_VP8D = (1 << 3),
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RK3288_VPU_CODEC_VP8E = (1 << 4),
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};
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#define ROCKCHIP_VPU_DECODERS (RK3288_VPU_CODEC_H264D | RK3288_VPU_CODEC_VP8D)
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#define ROCKCHIP_VPU_ENCODERS (RK3288_VPU_CODEC_H264E | RK3288_VPU_CODEC_VP8E)
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#define RK3288_CODECS (RK_VPU_CODEC_NONE | RK3288_VPU_CODEC_H264D | RK3288_VPU_CODEC_H264E | RK3288_VPU_CODEC_VP8D | RK3288_VPU_CODEC_VP8E)
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/**
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* enum rockchip_vpu_plane - indices of planes inside a VB2 buffer.
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* @PLANE_Y: Plane containing luminance data (also denoted as Y).
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* @PLANE_CB_CR: Plane containing interleaved chrominance data (also
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* denoted as CbCr).
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* @PLANE_CB: Plane containing CB part of chrominance data.
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* @PLANE_CR: Plane containing CR part of chrominance data.
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*/
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enum rockchip_vpu_plane {
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PLANE_Y = 0,
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PLANE_CB_CR = 1,
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PLANE_CB = 1,
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PLANE_CR = 2,
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};
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/**
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* struct rockchip_vpu_vp8e_buf_data - mode-specific per-buffer data
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* @dct_offset: Offset inside the buffer to DCT partition.
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* @hdr_size: Size of header data in the buffer.
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* @ext_hdr_size: Size of ext header data in the buffer.
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* @dct_size: Size of DCT partition in the buffer.
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* @header: Frame header to copy to destination buffer.
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*/
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struct rockchip_vpu_vp8e_buf_data {
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size_t dct_offset;
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size_t hdr_size;
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size_t ext_hdr_size;
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size_t dct_size;
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u8 header[ROCKCHIP_HEADER_SIZE];
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};
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/**
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* struct rockchip_vpu_h264e_buf_data - mode-specific per-buffer data
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* @sps_size: Size of sps data in the buffer.
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* @pps_size: Size of pps data in the buffer.
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* @slices_size: Size of slices data in the buffer.
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*/
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struct rockchip_vpu_h264e_buf_data {
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size_t sps_size;
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size_t pps_size;
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size_t slices_size;
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};
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/**
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* struct rockchip_vpu_buf - Private data related to each VB2 buffer.
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* @vb: Pointer to related VB2 buffer.
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* @list: List head for queuing in buffer queue.
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*/
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struct rockchip_vpu_buf {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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/* Mode-specific data. */
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union {
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struct rockchip_vpu_h264e_buf_data h264e;
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struct rockchip_vpu_vp8e_buf_data vp8e;
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};
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};
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/**
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* enum rockchip_vpu_state - bitwise flags indicating hardware state.
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* @VPU_RUNNING: The hardware has been programmed for operation
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* and is running at the moment.
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* @VPU_SUSPENDED: System is entering sleep state and no more runs
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* should be executed on hardware.
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*/
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enum rockchip_vpu_state {
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VPU_RUNNING = BIT(0),
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VPU_SUSPENDED = BIT(1),
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};
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/**
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* struct rockchip_vpu_dev - driver data
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* @v4l2_dev: V4L2 device to register video devices for.
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* @vfd_dec: Video device for decoder.
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* @vfd_enc: Video device for encoder.
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* @pdev: Pointer to VPU platform device.
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* @dev: Pointer to device for convenient logging using
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* dev_ macros.
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* @alloc_ctx: VB2 allocator context
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* (for allocations without kernel mapping).
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* @alloc_ctx_vm: VB2 allocator context
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* (for allocations with kernel mapping).
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* @aclk: Handle of ACLK clock.
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* @hclk: Handle of HCLK clock.
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* @base: Mapped address of VPU registers.
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* @enc_base: Mapped address of VPU encoder register for convenience.
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* @dec_base: Mapped address of VPU decoder register for convenience.
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* @mapping: DMA IOMMU mapping.
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* @domain: DMA IOMMU domain.
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* @vpu_mutex: Mutex to synchronize V4L2 calls.
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* @irqlock: Spinlock to synchronize access to data structures
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* shared with interrupt handlers.
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* @state: Device state.
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* @ready_ctxs: List of contexts ready to run.
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* @variant: Hardware variant-specfic parameters.
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* @current_ctx: Context being currently processed by hardware.
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* @run_wq: Wait queue to wait for run completion.
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* @watchdog_work: Delayed work for hardware timeout handling.
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* @dummy_encode_ctx: Context used to run dummy frame encoding to initialize
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* encoder hardware state.
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* @dummy_encode_src: Source buffers used for dummy frame encoding.
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* @dummy_encode_dst: Desintation buffer used for dummy frame encoding.
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* @was_decoding: Indicates whether last run context was a decoder.
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*/
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struct rockchip_vpu_dev {
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struct v4l2_device v4l2_dev;
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struct video_device *vfd_dec;
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struct video_device *vfd_enc;
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struct platform_device *pdev;
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struct device *dev;
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void *alloc_ctx;
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void *alloc_ctx_vm;
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struct clk *aclk;
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struct clk *hclk;
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void __iomem *base;
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void __iomem *enc_base;
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void __iomem *dec_base;
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struct dma_iommu_mapping *mapping;
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struct iommu_domain *domain;
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struct mutex vpu_mutex; /* video_device lock */
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spinlock_t irqlock;
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unsigned long state;
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struct list_head ready_ctxs;
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const struct rockchip_vpu_variant *variant;
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struct rockchip_vpu_ctx *current_ctx;
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wait_queue_head_t run_wq;
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struct delayed_work watchdog_work;
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struct rockchip_vpu_ctx *dummy_encode_ctx;
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struct rockchip_vpu_aux_buf dummy_encode_src[VIDEO_MAX_PLANES];
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struct rockchip_vpu_aux_buf dummy_encode_dst;
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bool was_decoding;
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};
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/**
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* struct rockchip_vpu_run_ops - per context operations on run data.
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* @prepare_run: Called when the context was selected for running
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* to prepare operating mode specific data.
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* @run_done: Called when hardware completed the run to collect
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* operating mode specific data from hardware and
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* finalize the processing.
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*/
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struct rockchip_vpu_run_ops {
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void (*prepare_run)(struct rockchip_vpu_ctx *);
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void (*run_done)(struct rockchip_vpu_ctx *, enum vb2_buffer_state);
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};
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/**
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* struct rockchip_vpu_vp8e_run - per-run data specific to VP8 encoding.
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* @reg_params: Pointer to a buffer containing register values prepared
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* by user space.
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*/
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struct rockchip_vpu_vp8e_run {
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const struct rockchip_reg_params *reg_params;
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};
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/**
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* struct rockchip_vpu_vp8d_run - per-run data specific to VP8 decoding.
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* @frame_hdr: Pointer to a buffer containing per-run frame data which
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* is needed by setting vpu register.
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*/
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struct rockchip_vpu_vp8d_run {
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const struct v4l2_ctrl_vp8_frame_hdr *frame_hdr;
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};
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/**
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* struct rockchip_vpu_h264d_run - per-run data specific to H264 decoding.
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* @sps: Pointer to a buffer containing H264 SPS.
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* @pps: Pointer to a buffer containing H264 PPS.
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* @scaling_matrix: Pointer to a buffer containing scaling matrix.
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* @slice_param: Pointer to a buffer containing slice parameters array.
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* @decode_param: Pointer to a buffer containing decode parameters.
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* @dpb: Array of DPB entries reordered to keep POC order.
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* @dpb_map: Map of indices used in ref_pic_list_* into indices to
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* reordered DPB array.
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*/
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struct rockchip_vpu_h264d_run {
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const struct v4l2_ctrl_h264_sps *sps;
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const struct v4l2_ctrl_h264_pps *pps;
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const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;
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const struct v4l2_ctrl_h264_slice_param *slice_param;
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const struct v4l2_ctrl_h264_decode_param *decode_param;
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struct v4l2_h264_dpb_entry dpb[16];
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u8 dpb_map[16];
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};
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/* struct for assemble bitstream */
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struct stream_s {
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u8 *buffer; /* point to first byte of stream */
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u8 *stream; /* Pointer to next byte of stream */
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u32 size; /* Byte size of stream buffer */
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u32 byte_cnt; /* Byte counter */
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u32 bit_cnt; /* Bit counter */
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u32 byte_buffer; /* Byte buffer */
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u32 buffered_bits; /* Amount of bits in byte buffer, [0-7] */
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s32 overflow; /* This will signal a buffer overflow */
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};
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void stream_put_bits(struct stream_s *buffer, s32 value, s32 number,
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const char *name);
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void stream_buffer_reset(struct stream_s *buffer);
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int stream_buffer_init(struct stream_s *buffer, u8 *stream, s32 size);
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/**
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* struct rockchip_vpu_h264e_run - per-run data specific to H264 encoding.
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*/
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struct rockchip_vpu_h264e_run {
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const struct rockchip_reg_params *reg_params;
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struct stream_s sps;
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struct stream_s pps;
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u32 hw_write_offset;
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};
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/**
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* struct rockchip_vpu_run - per-run data for hardware code.
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* @src: Source buffer to be processed.
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* @dst: Destination buffer to be processed.
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* @priv_src: Hardware private source buffer.
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* @priv_dst: Hardware private destination buffer.
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*/
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struct rockchip_vpu_run {
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/* Generic for more than one operating mode. */
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struct rockchip_vpu_buf *src;
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struct rockchip_vpu_buf *dst;
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struct rockchip_vpu_aux_buf priv_src;
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struct rockchip_vpu_aux_buf priv_dst;
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/* Specific for particular operating modes. */
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union {
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struct rockchip_vpu_vp8e_run vp8e;
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struct rockchip_vpu_vp8d_run vp8d;
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struct rockchip_vpu_h264d_run h264d;
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struct rockchip_vpu_h264e_run h264e;
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/* Other modes will need different data. */
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};
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};
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/**
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* struct rockchip_vpu_ctx - Context (instance) private data.
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*
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* @dev: VPU driver data to which the context belongs.
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* @fh: V4L2 file handler.
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*
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* @vpu_src_fmt: Descriptor of active source format.
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* @src_fmt: V4L2 pixel format of active source format.
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* @vpu_dst_fmt: Descriptor of active destination format.
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* @dst_fmt: V4L2 pixel format of active destination format.
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*
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* @vq_src: Videobuf2 source queue.
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* @src_queue: Internal source buffer queue.
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* @src_crop: Configured source crop rectangle (encoder-only).
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* @vq_dst: Videobuf2 destination queue
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* @dst_queue: Internal destination buffer queue.
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* @dst_bufs: Private buffers wrapping VB2 buffers (destination).
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*
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* @ctrls: Array containing pointer to registered controls.
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* @ctrl_handler: Control handler used to register controls.
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* @num_ctrls: Number of registered controls.
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*
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* @list: List head for queue of ready contexts.
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*
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* @run: Structure containing data about currently scheduled
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* processing run.
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* @run_ops: Set of operations related to currently scheduled run.
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* @hw: Structure containing hardware-related context.
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*/
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struct rockchip_vpu_ctx {
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struct rockchip_vpu_dev *dev;
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struct v4l2_fh fh;
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/* Format info */
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struct rockchip_vpu_fmt *vpu_src_fmt;
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struct v4l2_pix_format_mplane src_fmt;
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struct rockchip_vpu_fmt *vpu_dst_fmt;
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struct v4l2_pix_format_mplane dst_fmt;
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/* VB2 queue data */
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struct vb2_queue vq_src;
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struct list_head src_queue;
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struct v4l2_rect src_crop;
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struct vb2_queue vq_dst;
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struct list_head dst_queue;
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struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME];
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/* Controls */
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struct v4l2_ctrl *ctrls[ROCKCHIP_VPU_MAX_CTRLS];
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struct v4l2_ctrl_handler ctrl_handler;
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unsigned num_ctrls;
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/* Various runtime data */
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struct list_head list;
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struct rockchip_vpu_run run;
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const struct rockchip_vpu_run_ops *run_ops;
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struct rockchip_vpu_hw_ctx hw;
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};
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/**
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* struct rockchip_vpu_fmt - information about supported video formats.
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* @name: Human readable name of the format.
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* @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
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* @codec_mode: Codec mode related to this format. See
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* enum rockchip_vpu_codec_mode.
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* @num_planes: Number of planes used by this format.
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* @depth: Depth of each plane in bits per pixel.
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* @enc_fmt: Format identifier for encoder registers.
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*/
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struct rockchip_vpu_fmt {
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char *name;
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u32 fourcc;
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enum rockchip_vpu_codec_mode codec_mode;
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int num_planes;
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u8 depth[VIDEO_MAX_PLANES];
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enum rockchip_vpu_enc_fmt enc_fmt;
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};
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/**
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* struct rockchip_vpu_control - information about controls to be registered.
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* @id: Control ID.
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* @type: Type of the control.
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* @name: Human readable name of the control.
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* @minimum: Minimum value of the control.
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* @maximum: Maximum value of the control.
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* @step: Control value increase step.
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* @menu_skip_mask: Mask of invalid menu positions.
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* @default_value: Initial value of the control.
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* @max_stores: Maximum number of configration stores.
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* @dims: Size of each dimension of compound control.
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* @elem_size: Size of individual element of compound control.
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* @is_volatile: Control is volatile.
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* @is_read_only: Control is read-only.
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* @can_store: Control uses configuration stores.
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*
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* See also struct v4l2_ctrl_config.
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*/
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struct rockchip_vpu_control {
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u32 id;
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enum v4l2_ctrl_type type;
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const char *name;
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s32 minimum;
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s32 maximum;
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s32 step;
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u32 menu_skip_mask;
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s32 default_value;
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s32 max_stores;
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u32 dims[V4L2_CTRL_MAX_DIMS];
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u32 elem_size;
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bool is_volatile:1;
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bool is_read_only:1;
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bool can_store:1;
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};
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/* Logging helpers */
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/**
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* debug - Module parameter to control level of debugging messages.
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*
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* Level of debugging messages can be controlled by bits of module parameter
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* called "debug". Meaning of particular bits is as follows:
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*
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* bit 0 - global information: mode, size, init, release
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* bit 1 - each run start/result information
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* bit 2 - contents of small controls from userspace
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* bit 3 - contents of big controls from userspace
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* bit 4 - detail fmt, ctrl, buffer q/dq information
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* bit 5 - detail function enter/leave trace information
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* bit 6 - register write/read information
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*/
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extern int debug;
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#define vpu_debug(level, fmt, args...) \
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do { \
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if (debug & BIT(level)) \
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pr_debug("%s:%d: " fmt, \
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__func__, __LINE__, ##args); \
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} while (0)
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#define vpu_debug_enter() vpu_debug(5, "enter\n")
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#define vpu_debug_leave() vpu_debug(5, "leave\n")
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#define vpu_err(fmt, args...) \
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pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
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static inline char *fmt2str(u32 fmt, char *str)
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{
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char a = fmt & 0xFF;
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char b = (fmt >> 8) & 0xFF;
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char c = (fmt >> 16) & 0xFF;
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char d = (fmt >> 24) & 0xFF;
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sprintf(str, "%c%c%c%c", a, b, c, d);
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return str;
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}
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/* Structure access helpers. */
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static inline struct rockchip_vpu_ctx *fh_to_ctx(struct v4l2_fh *fh)
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{
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return container_of(fh, struct rockchip_vpu_ctx, fh);
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}
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static inline struct rockchip_vpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
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{
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return container_of(ctrl->handler,
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struct rockchip_vpu_ctx, ctrl_handler);
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}
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static inline struct rockchip_vpu_buf *vb_to_buf(struct vb2_buffer *vb)
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{
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return container_of(to_vb2_v4l2_buffer(vb),
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struct rockchip_vpu_buf, vb);
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}
|
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static inline bool rockchip_vpu_ctx_is_encoder(struct rockchip_vpu_ctx *ctx)
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{
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return ctx->vpu_dst_fmt->codec_mode != RK_VPU_CODEC_NONE;
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}
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static inline bool
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rockchip_vpu_ctx_is_dummy_encode(struct rockchip_vpu_ctx *ctx)
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{
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struct rockchip_vpu_dev *dev = ctx->dev;
|
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return ctx == dev->dummy_encode_ctx;
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}
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static inline bool
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rockchip_vpu_dev_codec_support(struct rockchip_vpu_dev *dev,
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enum rockchip_vpu_codec_mode codec_mode)
|
{
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return !!(codec_mode & dev->variant->codecs);
|
}
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int rockchip_vpu_ctrls_setup(struct rockchip_vpu_ctx *ctx,
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const struct v4l2_ctrl_ops *ctrl_ops,
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struct rockchip_vpu_control *controls,
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unsigned num_ctrls,
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const char *const *(*get_menu)(u32));
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void rockchip_vpu_ctrls_delete(struct rockchip_vpu_ctx *ctx);
|
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void rockchip_vpu_try_context(struct rockchip_vpu_dev *dev,
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struct rockchip_vpu_ctx *ctx);
|
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void rockchip_vpu_run_done(struct rockchip_vpu_ctx *ctx,
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enum vb2_buffer_state result);
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int rockchip_vpu_aux_buf_alloc(struct rockchip_vpu_dev *vpu,
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struct rockchip_vpu_aux_buf *buf, size_t size);
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void rockchip_vpu_aux_buf_free(struct rockchip_vpu_dev *vpu,
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struct rockchip_vpu_aux_buf *buf);
|
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/* Register accessors. */
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static inline void vepu_write_relaxed(struct rockchip_vpu_dev *vpu,
|
u32 val, u32 reg)
|
{
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vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
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writel_relaxed(val, vpu->enc_base + reg);
|
}
|
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static inline void vepu_write(struct rockchip_vpu_dev *vpu, u32 val, u32 reg)
|
{
|
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
|
writel(val, vpu->enc_base + reg);
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}
|
|
static inline u32 vepu_read(struct rockchip_vpu_dev *vpu, u32 reg)
|
{
|
u32 val = readl(vpu->enc_base + reg);
|
|
vpu_debug(6, "MARK: get reg[%03d]: %08x\n", reg / 4, val);
|
return val;
|
}
|
|
static inline void vdpu_write_relaxed(struct rockchip_vpu_dev *vpu,
|
u32 val, u32 reg)
|
{
|
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
|
writel_relaxed(val, vpu->dec_base + reg);
|
}
|
|
static inline void vdpu_write(struct rockchip_vpu_dev *vpu, u32 val, u32 reg)
|
{
|
vpu_debug(6, "MARK: set reg[%03d]: %08x\n", reg / 4, val);
|
writel(val, vpu->dec_base + reg);
|
}
|
|
static inline u32 vdpu_read(struct rockchip_vpu_dev *vpu, u32 reg)
|
{
|
u32 val = readl(vpu->dec_base + reg);
|
|
vpu_debug(6, "MARK: get reg[%03d]: %08x\n", reg / 4, val);
|
return val;
|
}
|
|
#endif /* ROCKCHIP_VPU_COMMON_H_ */
|
