/* SPDX-License-Identifier: GPL-2.0 */
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/********************************************************************************
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*
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* Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
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* Module : video_eq.h
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* Description :
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* Author :
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* Date :
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* Version : Version 1.0
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*
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********************************************************************************
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* History :
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*
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*
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********************************************************************************/
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#ifndef _JAGUAR1_VIDEO_EQ_H_
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#define _JAGUAR1_VIDEO_EQ_H_
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#include "jaguar1_common.h"
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typedef struct _video_equalizer_hsync_stage_s{
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unsigned int hsync_stage[6];
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}video_equalizer_hsync_stage_s;
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typedef struct _video_equalizer_agc_stage_s{
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unsigned int agc_stage[6];
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}video_equalizer_agc_stage_s;
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typedef struct _video_equalizer_distance_table_s{
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video_equalizer_hsync_stage_s hsync_stage;
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video_equalizer_agc_stage_s agc_stage;
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} video_equalizer_distance_table_s;
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typedef struct _video_equalizer_base_s{
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unsigned char eq_bypass[11]; // B5x01
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unsigned char eq_band_sel[11]; // B5x58
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unsigned char eq_gain_sel[11]; // B5x5C
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unsigned char deq_a_on[11]; // BAx3d
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unsigned char deq_a_sel[11]; // BAx3C
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} video_equalizer_base_s;
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typedef struct _video_equalizer_coeff_s{
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unsigned char deqA_01[11]; // BankA 0x30
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unsigned char deqA_02[11]; // BankA 0x31
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unsigned char deqA_03[11]; // BankA 0x32
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unsigned char deqA_04[11]; // BankA 0x33
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unsigned char deqA_05[11]; // BankA 0x34
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unsigned char deqA_06[11]; // BankA 0x35
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unsigned char deqA_07[11]; // BankA 0x36
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unsigned char deqA_08[11]; // BankA 0x37
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unsigned char deqA_09[11]; // BankA 0x38
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unsigned char deqA_10[11]; // BankA 0x39
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unsigned char deqA_11[11]; // BankA 0x3A
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unsigned char deqA_12[11]; // BankA 0x3B
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} video_equalizer_coeff_s;
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typedef struct _video_equalizer_color_s{
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unsigned char contrast[11]; // Bank0 0x10
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unsigned char y_peaking_mode[11]; // Bank0 0x18
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unsigned char y_fir_mode [11];
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unsigned char c_filter[11]; // Bank0 0x21
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unsigned char pal_cm_off[11]; // Bank0 0x21
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unsigned char hue[11]; // Bank0 0x40
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unsigned char u_gain[11]; // Bank0 0x44
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unsigned char v_gain[11]; // Bank0 0x48
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unsigned char u_offset[11]; // Bank0 0x4c
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unsigned char v_offset[11]; // Bank0 0x50
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unsigned char black_level[11]; // Bank5 0x20
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unsigned char acc_ref[11]; // Bank5 0x27
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unsigned char cti_delay[11]; // Bank5 0x28
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unsigned char saturation_b[11]; // Bank5 0x2B
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unsigned char burst_dec_a[11]; // Bank5 0x24
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unsigned char burst_dec_b[11]; // Bank5 0x5F
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unsigned char burst_dec_c[11]; // Bank5 0xD1
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unsigned char c_option[11]; // Bank5 0xD5
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unsigned char y_filter_b[11]; // BankA 0x25
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unsigned char y_filter_b_sel[11]; // BankA 0x27
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} video_equalizer_color_s;
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typedef struct _video_equalizer_timing_a_s{
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unsigned char h_delay_a[11]; // Bank0 0x58
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unsigned char h_delay_b[11]; // Bank0 0x89
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unsigned char h_delay_c[11]; // Bank0 0x8E
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unsigned char y_delay[11]; // Bank0 0xA0
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} video_equalizer_timing_a_s;
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typedef struct _video_equalizer_clk_s{
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unsigned char clk_adc_pre[11]; // Bank1 0x84
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unsigned char clk_adc_post[11]; // Bank1 0x8C
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unsigned char clk_adc[11]; // Bank1 0x8C
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} video_equalizer_clk_s;
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typedef struct _video_equalizer_timing_b_s{
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unsigned char h_scaler1[11]; // B9x96 + ch*0x20
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unsigned char h_scaler2[11]; // B9x97 + ch*0x20
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unsigned char h_scaler3[11]; // B9x98 + ch*0x20
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unsigned char h_scaler4[11]; // B9x99 + ch*0x20
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unsigned char h_scaler5[11]; // B9x9a + ch*0x20
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unsigned char h_scaler6[11]; // B9x9b + ch*0x20
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unsigned char h_scaler7[11]; // B9x9c + ch*0x20
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unsigned char h_scaler8[11]; // B9x9d + ch*0x20
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unsigned char h_scaler9[11]; // B9x9e + ch*0x20
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unsigned char pn_auto[11]; // B9x40 + ch
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unsigned char comb_mode[11]; // B5x90
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unsigned char h_pll_op_a[11]; // B5xB9
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unsigned char mem_path[11]; // B5x57
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unsigned char fsc_lock_speed[11]; //B5x25
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unsigned char ahd_mode[11];
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unsigned char sd_mode[11];
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unsigned char spl_mode[11];
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unsigned char vblk_end[11];
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unsigned char afe_g_sel[11];
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unsigned char afe_ctr_clp[11];
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unsigned char d_agc_option[11];
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} video_equalizer_timing_b_s;
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typedef struct _video_equalizer_value_table_s{
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video_equalizer_base_s eq_base;
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video_equalizer_coeff_s eq_coeff;
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video_equalizer_color_s eq_color;
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video_equalizer_timing_a_s eq_timing_a;
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video_equalizer_clk_s eq_clk;
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video_equalizer_timing_b_s eq_timing_b;
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} video_equalizer_value_table_s;
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typedef struct _jaguar1_video_eq_value_table_s{
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char *name;
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NC_VIVO_CH_FORMATDEF video_fmt;
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NC_ANALOG_INPUT analog_input;
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video_equalizer_base_s eq_base;
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video_equalizer_coeff_s eq_coeff;
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video_equalizer_color_s eq_color;
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video_equalizer_timing_a_s eq_timing_a;
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video_equalizer_clk_s eq_clk;
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video_equalizer_timing_b_s eq_timing_b;
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} _jaguar1_video_eq_value_table_s;
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typedef struct _video_equalizer_info{
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unsigned char Ch;
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unsigned char devnum;
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unsigned char stage;
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unsigned char FmtDef;
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unsigned char Cable;
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unsigned char Input;
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} video_equalizer_info_s;
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void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set);
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void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set);
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void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set);
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#endif /* _JAGUAR1_VIDEO_EQ_H_ */
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