// SPDX-License-Identifier: GPL-2.0
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/********************************************************************************
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*
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* Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
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* Module : video_auto_detect.c
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* Description :
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* Author :
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* Date :
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* Version : Version 1.0
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*
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********************************************************************************
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* History :
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*
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*
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********************************************************************************/
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#include <linux/string.h>
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#include <linux/delay.h>
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#include "jaguar1_common.h"
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#include "jaguar1_video_eq.h"
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#include "jaguar1_cableA_video_eq_table.h"
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#include "jaguar1_reg_set_def.h"
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#include "jaguar1_video.h"
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//extern unsigned int jaguar1_i2c_addr[4];
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static NC_JAGUAR1_EQ NC_VD_EQ_FindFormatDef( NC_VIVO_CH_FORMATDEF format_standard, NC_ANALOG_INPUT analog_input )
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{
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int ii;
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for(ii=0;ii<NC_EQ_SETTING_FMT_MAX;ii++)
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{
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_jaguar1_video_eq_value_table_s *pFmt = &equalizer_value_fmtdef_cableA[ ii ];
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if( pFmt->video_fmt == format_standard )
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if( pFmt->analog_input == analog_input )
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return ii;
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}
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printk("NC_VD_EQ_FindFormatDef UNKNOWN format!!!\n");
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return NC_EQ_SETTING_FMT_UNKNOWN;
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}
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static void __eq_base_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_base_s *pbase )
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{
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unsigned char ch = pvin_eq_set->Ch;
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unsigned char dist = pvin_eq_set->stage;
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REG_SET_5x65_0_8_EQ_BYPASS( ch, pbase->eq_bypass[dist] );
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REG_SET_5x58_0_8_EQ_BAND_SEL( ch, pbase->eq_band_sel[dist] );
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REG_SET_5x5C_0_8_EQ_GAIN_SEL( ch, pbase->eq_gain_sel[dist] );
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REG_SET_Ax3D_0_8_EQ_DEQ_A_ON( ch, pbase->deq_a_on[dist] );
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REG_SET_Ax3C_0_8_EQ_DEQ_A_SEL( ch, pbase->deq_a_sel[dist] );
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}
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static void __eq_coeff_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_coeff_s *pcoeff )
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{
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unsigned char ch = pvin_eq_set->Ch;
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unsigned char dist = pvin_eq_set->stage;
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REG_SET_Ax30_0_8_EQ_DEQ_A_01( ch, pcoeff->deqA_01[dist] );
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REG_SET_Ax31_0_8_EQ_DEQ_A_02( ch, pcoeff->deqA_02[dist] );
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REG_SET_Ax32_0_8_EQ_DEQ_A_03( ch, pcoeff->deqA_03[dist] );
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REG_SET_Ax33_0_8_EQ_DEQ_A_04( ch, pcoeff->deqA_04[dist] );
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REG_SET_Ax34_0_8_EQ_DEQ_A_05( ch, pcoeff->deqA_05[dist] );
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REG_SET_Ax35_0_8_EQ_DEQ_A_06( ch, pcoeff->deqA_06[dist] );
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REG_SET_Ax36_0_8_EQ_DEQ_A_07( ch, pcoeff->deqA_07[dist] );
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REG_SET_Ax37_0_8_EQ_DEQ_A_08( ch, pcoeff->deqA_08[dist] );
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REG_SET_Ax38_0_8_EQ_DEQ_A_09( ch, pcoeff->deqA_09[dist] );
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REG_SET_Ax39_0_8_EQ_DEQ_A_10( ch, pcoeff->deqA_10[dist] );
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REG_SET_Ax3A_0_8_EQ_DEQ_A_11( ch, pcoeff->deqA_11[dist] );
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REG_SET_Ax3B_0_8_EQ_DEQ_A_12( ch, pcoeff->deqA_12[dist] );
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}
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static void __eq_color_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_color_s *pcolor )
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{
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unsigned char ch = pvin_eq_set->Ch;
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unsigned char dist = pvin_eq_set->stage;
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REG_SET_0x24_0_8_EQ_COLOR_CONTRAST( ch, pcolor->contrast[dist] );
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REG_SET_0x30_0_8_EQ_COLOR_H_PEAKING_1( ch, pcolor->y_peaking_mode[dist] );
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REG_SET_0x34_0_8_EQ_COLOR_H_PEAKING_2( ch, pcolor->y_fir_mode[dist] );
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REG_SET_5x31_0_8_EQ_COLOR_C_FILTER( ch, pcolor->c_filter[dist] );
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REG_SET_0x5c_0_8_EQ_PAL_CM_OFF( ch, pcolor->pal_cm_off[dist] );
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REG_SET_0x40_0_8_EQ_COLOR_HUE( ch, pcolor->hue[dist] );
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REG_SET_0x44_0_8_EQ_COLOR_U_GAIN( ch, pcolor->u_gain[dist] );
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REG_SET_0x48_0_8_EQ_COLOR_V_GAIN( ch, pcolor->v_gain[dist] );
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REG_SET_0x4C_0_8_EQ_COLOR_U_OFFSET( ch, pcolor->u_offset[dist] );
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REG_SET_0x50_0_8_EQ_COLOR_V_OFFSET( ch, pcolor->v_offset[dist] );
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REG_SET_0x28_0_8_EQ_COLOR_BLACK_LEVEL( ch, pcolor->black_level[dist] );
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REG_SET_5x27_0_8_EQ_COLOR_ACC_REF( ch, pcolor->acc_ref[dist] );
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REG_SET_5x28_0_8_EQ_COLOR_CTI_DELAY( ch, pcolor->cti_delay[dist] );
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REG_SET_5x2b_0_8_EQ_COLOR_SUB_SATURATION( ch, pcolor->saturation_b[dist] );
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REG_SET_5x24_0_8_EQ_COLOR_BURST_DEC_A( ch, pcolor->burst_dec_a[dist] );
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REG_SET_5x5F_0_8_EQ_COLOR_BURST_DEC_B( ch, pcolor->burst_dec_b[dist] );
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REG_SET_5xD1_0_8_EQ_COLOR_BURST_DEC_C( ch, pcolor->burst_dec_c[dist] );
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REG_SET_5xD5_0_8_EQ_COLOR_C_OPTION( ch, pcolor->c_option[dist] );
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REG_SET_Ax25_0_8_EQ_COLOR_Y_FILTER_B( ch, pcolor->y_filter_b[dist] );
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REG_SET_Ax27_0_8_EQ_COLOR_Y_FILTER_B_SEL( ch, pcolor->y_filter_b_sel[dist] );
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}
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static void __eq_timing_a_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_timing_a_s *ptiming_a )
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{
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unsigned char ch = pvin_eq_set->Ch;
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unsigned char dist = pvin_eq_set->stage;
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REG_SET_0x68_0_8_EQ_TIMING_A_H_DELAY_A(ch, ptiming_a->h_delay_a[dist] );
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REG_SET_5x38_0_8_EQ_TIMING_A_H_DELAY_B(ch, ptiming_a->h_delay_b[dist] );
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REG_SET_0x6C_0_4_EQ_TIMING_A_H_DELAY_C(ch, ptiming_a->h_delay_c[dist] );
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REG_SET_0x64_0_8_EQ_TIMING_A_Y_DELAY(ch , ptiming_a->y_delay[dist] );
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}
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static void __eq_clk_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_clk_s *pclk )
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{
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unsigned char ch = pvin_eq_set->Ch;
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unsigned char dist = pvin_eq_set->stage;
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REG_SET_1x84_0_8_EQ_CLOCK_ADC_CLK( ch, pclk->clk_adc[dist] );
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REG_SET_1x88_0_8_EQ_CLOCK_PRE_CLK( ch, pclk->clk_adc_pre[dist] );
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REG_SET_1x8C_0_8_EQ_CLOCK_POST_CLK( ch, pclk->clk_adc_post[dist] );
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}
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static void __eq_timing_b_set_value( video_equalizer_info_s *pvin_eq_set, video_equalizer_timing_b_s *ptiming_b )
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{
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unsigned char ch = pvin_eq_set->Ch;
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unsigned char dist = pvin_eq_set->stage;
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REG_SET_9x96_0_8_EQ_TIMING_B_HSCALER_1( ch, ptiming_b->h_scaler1[dist] );
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REG_SET_9x97_0_8_EQ_TIMING_B_HSCALER_2( ch, ptiming_b->h_scaler2[dist] );
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REG_SET_9x98_0_8_EQ_TIMING_B_HSCALER_3( ch, ptiming_b->h_scaler3[dist] );
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REG_SET_9x99_0_8_EQ_TIMING_B_HSCALER_4( ch, ptiming_b->h_scaler4[dist] );
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REG_SET_9x9A_0_8_EQ_TIMING_B_HSCALER_5( ch, ptiming_b->h_scaler5[dist] );
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REG_SET_9x9B_0_8_EQ_TIMING_B_HSCALER_6( ch, ptiming_b->h_scaler6[dist] );
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REG_SET_9x9C_0_8_EQ_TIMING_B_HSCALER_7( ch, ptiming_b->h_scaler7[dist] );
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REG_SET_9x9D_0_8_EQ_TIMING_B_HSCALER_8( ch, ptiming_b->h_scaler8[dist] );
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REG_SET_9x9E_0_8_EQ_TIMING_B_HSCALER_9( ch, ptiming_b->h_scaler9[dist] );
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REG_SET_9x40_0_8_EQ_TIMING_B_PN_AUTO( ch, ptiming_b->pn_auto[dist] );
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REG_SET_5x90_0_8_EQ_TIMINING_B_COMB_MODE( ch, ptiming_b->comb_mode[dist] );
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REG_SET_5xB9_0_8_EQ_TIMING_B_HPLL_OP_A( ch, ptiming_b->h_pll_op_a[dist] );
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REG_SET_5x57_0_8_EQ_TIMING_B_MEM_PATH( ch, ptiming_b->mem_path[dist] );
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REG_SET_5x25_0_8_EQ_TIMING_B_FSC_LOCK_SPD( ch, ptiming_b->fsc_lock_speed[dist] );
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REG_SET_0x04_0_8_EQ_TIMING_B_SD_MD( ch, ptiming_b->sd_mode[dist] );
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REG_SET_0x08_0_8_EQ_TIMING_B_AHD_MD( ch, ptiming_b->ahd_mode[dist] );
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REG_SET_0x0C_0_8_EQ_TIMING_B_SPECIAL_MD( ch, ptiming_b->spl_mode[dist] );
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REG_SET_0x78_0_8_EQ_TIMING_B_VBLK_END( ch, ptiming_b->vblk_end[dist] );
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REG_SET_5x1D_0_8_EQ_AFE_G_SEL( ch, ptiming_b->afe_g_sel[dist] );
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REG_SET_5x01_0_8_EQ_AFE_CTR_CLP( ch, ptiming_b->afe_ctr_clp[dist] );
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REG_SET_5x05_0_8_EQ_D_AGC_OPTION( ch, ptiming_b->d_agc_option[dist] );
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}
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void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set)
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{
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NC_JAGUAR1_EQ eq_fmt;
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unsigned char ch = pvin_eq_set->Ch;
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int fmt = pvin_eq_set->FmtDef;
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int input = pvin_eq_set->Input;
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int cable = pvin_eq_set->Cable;
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/* int stage = pvin_eq_set->stage; */
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_jaguar1_video_eq_value_table_s eq_value;
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// printk("[drv_eq]ch%d >> fmt(%d) cable(%d) stage(%d) input(%d)\n", ch, fmt, cable, stage, input);
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eq_fmt = NC_VD_EQ_FindFormatDef( fmt, input );
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if( cable == CABLE_A )
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eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
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else if( cable == CABLE_B )
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eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
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else if( cable == CABLE_C )
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eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
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else if( cable == CABLE_D )
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eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
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else
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eq_value = (_jaguar1_video_eq_value_table_s)equalizer_value_fmtdef_cableA[eq_fmt];
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if( eq_value.name == NULL )
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{
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printk("[drv_eq]Error - Unknown EQ Table!!\n");
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return;
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}
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else
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{
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/* set_eq_value */
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__eq_base_set_value( pvin_eq_set, &eq_value.eq_base );
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__eq_coeff_set_value( pvin_eq_set, &eq_value.eq_coeff );
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__eq_color_set_value( pvin_eq_set, &eq_value.eq_color);
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__eq_timing_a_set_value( pvin_eq_set, &eq_value.eq_timing_a );
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__eq_clk_set_value( pvin_eq_set, &eq_value.eq_clk );
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__eq_timing_b_set_value( pvin_eq_set, &eq_value.eq_timing_b );
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if( AHD20_SD_H960_2EX_Btype_NT_SINGLE_ENDED || AHD20_SD_H960_2EX_Btype_NT_DIFFERENTIAL )
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{
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}
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else if( AHD20_SD_H960_2EX_Btype_PAL_SINGLE_ENDED || AHD20_SD_H960_2EX_Btype_PAL_DIFFERENTIAL )
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{
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}
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else
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{
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}
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printk("[drv_eq]ch::%d >>> fmt::%s\n", ch, eq_value.name);
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}
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}
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void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set)
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{
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unsigned char ch = pvin_eq_set->Ch;
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int cable = pvin_eq_set->Cable;
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printk("[DRV]video_input_eq_cable_set::ch(%d) cable(%d)\n", ch, cable );
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}
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void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set)
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{
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unsigned char ch = pvin_eq_set->Ch;
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int input = pvin_eq_set->Input;
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REG_SET_0x18_0_8_EX_CBAR_ON( ch, 0x13 );
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if( input == DIFFERENTIAL )
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{
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REG_SET_5x00_0_8_CMP( ch, 0xd0 );
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REG_SET_5x01_0_8_CML( ch, 0x2c );
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REG_SET_5x1D_0_8_AFE( ch, 0x8c );
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REG_SET_5x92_0_8_PWM( ch, 0x00 );
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}
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else if( input == SINGLE_ENDED )
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{
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REG_SET_5x00_0_8_CMP( ch, 0xd0 );
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REG_SET_5x01_0_8_CML( ch, 0xa2 );
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// REG_SET_5x1D_0_8_AFE( ch, 0x00 );
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REG_SET_5x92_0_8_PWM( ch, 0x00 );
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}
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else
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{
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printk("Jaguar1 Analog Input Setting Fail !!!\n");
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}
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printk("[DRV]video_input_eq_analog_input_set::ch(%d) input(%d)\n", ch, input );
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}
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