// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include <dt-bindings/clock/rk618-cru.h>
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#include "px30-ad-r35-mb.dtsi"
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&dmc {
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auto-freq-en = <0>;
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};
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&i2c0 {
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status = "okay";
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rk618@50 {
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compatible = "rockchip,rk618";
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reg = <0x50>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_2ch_mclk>;
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clocks = <&cru SCLK_I2S1_OUT>;
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clock-names = "clkin";
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assigned-clocks = <&cru SCLK_I2S1_OUT>;
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assigned-clock-rates = <11289600>;
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reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
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status = "okay";
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clock: cru {
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compatible = "rockchip,rk618-cru";
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clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
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clock-names = "clkin", "lcdc0_dclkp";
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assigned-clocks = <&clock SCALER_PLLIN_CLK>,
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<&clock VIF_PLLIN_CLK>,
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<&clock SCALER_CLK>,
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<&clock VIF0_PRE_CLK>,
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<&clock CODEC_CLK>,
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<&clock DITHER_CLK>;
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assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
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<&clock LCDC0_CLK>,
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<&clock SCALER_PLL_CLK>,
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<&clock VIF_PLL_CLK>,
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<&cru SCLK_I2S1_OUT>,
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<&clock VIF0_CLK>;
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#clock-cells = <1>;
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status = "okay";
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};
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hdmi {
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compatible = "rockchip,rk618-hdmi";
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clocks = <&clock HDMI_CLK>;
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clock-names = "hdmi";
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assigned-clocks = <&clock HDMI_CLK>;
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assigned-clock-parents = <&clock VIF0_CLK>;
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interrupt-parent = <&gpio2>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_hdmi>;
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};
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};
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};
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};
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};
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};
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&vopl {
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assigned-clocks = <&cru PLL_NPLL>;
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assigned-clock-rates = <1188000000>;
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};
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&rgb {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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rgb_out_hdmi: endpoint {
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remote-endpoint = <&hdmi_in_rgb>;
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};
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};
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};
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};
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&rgb_in_vopb {
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status = "disabled";
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};
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&rgb_in_vopl {
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status = "okay";
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};
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&route_rgb {
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connect = <&vopl_out_rgb>;
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status = "okay";
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};
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