* ROCKCHIP type-c PHY
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---------------------
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Required properties:
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- compatible : must be "rockchip,rk3399-typec-phy"
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- reg: Address and length of the usb phy control register set
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- rockchip,grf : phandle to the syscon managing the "general
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register files"
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- clocks : phandle + clock specifier for the phy clocks
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- clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
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- assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
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<&cru SCLK_UPHY1_TCPDCORE>;
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- assigned-clock-rates : the phy core clk frequency, shall be: 50000000
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- resets : a list of phandle + reset specifier pairs
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- reset-names : string reset name, must be:
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"uphy", "uphy-pipe", "uphy-tcphy"
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Optional properties:
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- extcon : extcon specifier for the Power Delivery
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- rockchip,phy-config : A list of voltage swing(mV) and pre-emphasis
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(dB) pairs. They are 3 blocks of 4 entries and
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correspond to s0p0 ~ s0p3, s1p0 ~ s1p3,
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s2p0 ~ s2p3, s3p0 ~ s2p3 swing and pre-emphasis
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values.
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Required nodes : a sub-node is required for each port the phy provides.
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The sub-node name is used to identify dp or usb3 port,
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and shall be the following entries:
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* "dp-port" : the name of DP port.
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* "usb3-port" : the name of USB3 port.
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Required properties (port (child) node):
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- #phy-cells : must be 0, See ./phy-bindings.txt for details.
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Deprecated properties, do not use in new device tree sources, these
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properties are determined by the compatible value:
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- rockchip,typec-conn-dir
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- rockchip,usb3tousb2-en
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- rockchip,external-psm
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- rockchip,pipe-status
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Example:
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tcphy0: phy@ff7c0000 {
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compatible = "rockchip,rk3399-typec-phy";
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reg = <0x0 0xff7c0000 0x0 0x40000>;
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rockchip,grf = <&grf>;
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extcon = <&fusb0>;
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clocks = <&cru SCLK_UPHY0_TCPDCORE>,
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<&cru SCLK_UPHY0_TCPDPHY_REF>;
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clock-names = "tcpdcore", "tcpdphy-ref";
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assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
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assigned-clock-rates = <50000000>;
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resets = <&cru SRST_UPHY0>,
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<&cru SRST_UPHY0_PIPE_L00>,
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<&cru SRST_P_UPHY0_TCPHY>;
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reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
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rockchip,phy-config = <0x2a 0x00>,
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<0x1f 0x15>,
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<0x14 0x22>,
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<0x02 0x2b>,
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<0x21 0x00>,
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<0x12 0x15>,
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<0x02 0x22>,
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<0 0>,
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<0x15 0x00>,
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<0x00 0x15>,
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<0 0>,
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<0 0>;
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tcphy0_dp: dp-port {
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#phy-cells = <0>;
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};
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tcphy0_usb3: usb3-port {
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#phy-cells = <0>;
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};
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};
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tcphy1: phy@ff800000 {
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compatible = "rockchip,rk3399-typec-phy";
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reg = <0x0 0xff800000 0x0 0x40000>;
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rockchip,grf = <&grf>;
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extcon = <&fusb1>;
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clocks = <&cru SCLK_UPHY1_TCPDCORE>,
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<&cru SCLK_UPHY1_TCPDPHY_REF>;
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clock-names = "tcpdcore", "tcpdphy-ref";
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assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
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assigned-clock-rates = <50000000>;
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resets = <&cru SRST_UPHY1>,
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<&cru SRST_UPHY1_PIPE_L00>,
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<&cru SRST_P_UPHY1_TCPHY>;
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reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
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rockchip,phy-config = <0x2a 0x00>,
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<0x1f 0x15>,
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<0x14 0x22>,
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<0x02 0x2b>,
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<0x21 0x00>,
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<0x12 0x15>,
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<0x02 0x22>,
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<0 0>,
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<0x15 0x00>,
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<0x00 0x15>,
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<0 0>,
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<0 0>;
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tcphy1_dp: dp-port {
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#phy-cells = <0>;
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};
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tcphy1_usb3: usb3-port {
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#phy-cells = <0>;
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};
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};
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