ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK
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Required properties (phy (parent) node):
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- compatible: should be one of the listed compatibles:
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* "rockchip,rk3328-u3phy"
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* "rockchip,rk322xh-u3phy"
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- reg : the base address of USB 3.0 PHY.
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- rockchip,u3phygrf : phandle to the syscon managing the
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"USB 3.0 PHY general register files".
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- interrupts : specify an interrupt for each entry in interrupt-names.
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- interrupt-names : a list which shall be the following entries:
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* "linestate" : for the host/otg linestate interrupt
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- clocks : phandle + clock specifier for the phy clocks.
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- clock-names :
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* "u3phy-otg" for USB 3.0 PHY utmi
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* "u3phy-pipe" for USB 3.0 PHY pipe
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- resets : a list of phandle + reset specifier pairs
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- reset-names :
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* "u3phy-u2-por" for the USB 2.0 logic of USB 3.0 PHY
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* "u3phy-u3-por" for the USB 3.0 logic of USB 3.0 PHY
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* "u3phy-pipe-mac" for the USB 3.0 PHY pipe MAC
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* "u3phy-utmi-mac" for the USB 3.0 PHY utmi MAC
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* "u3phy-utmi-apb" for the USB 3.0 PHY utmi apb
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* "u3phy-pipe-apb" for the USB 3.0 PHY pipe apb
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Optional properties:
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- vbus-supply: regulator phandle for vbus power source.
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Required nodes : a sub-node is required for USB 3.0 or USB 2.0 the phy provides.
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The sub-node name is used to identify phy type, and shall be
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the following entries:
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* "u3phy_utmi" : USB 2.0 utmi phy.
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* "u3phy_pipe" : USB 3.0 pipe phy.
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- #phy-cells : must be 0. See ./phy-bindings.txt for details.
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Optional properties for utmi node:
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- rockchip,odt-val-tuning : specify 45ohm ODT tuning value.
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Optional properties for pipe node:
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- rockchip,refclk-25m-quirk : phy reference clock changed to 25m quirk.
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Example:
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usb3phy_grf: syscon@ff460000 {
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compatible = "rockchip,usb3phy-grf", "syscon";
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reg = <0x0 0xff460000 0x0 0x1000>;
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};
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...
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u3phy: usb3-phy@ff470000 {
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compatible = "rockchip,rk3328-u3phy";
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reg = <0x0 0xff470000 0x0 0x0>;
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rockchip,u3phygrf = <&usb3phy_grf>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
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clock-names = "u3phy-otg", "u3phy-pipe";
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resets = <&cru SRST_USB3PHY_U2>,
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<&cru SRST_USB3PHY_U3>,
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<&cru SRST_USB3PHY_PIPE>,
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<&cru SRST_USB3OTG_UTMI>,
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<&cru SRST_USB3PHY_OTG_P>,
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<&cru SRST_USB3PHY_PIPE_P>;
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reset-names = "u3phy-u2-por", "u3phy-u3-por",
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"u3phy-pipe-mac", "u3phy-utmi-mac",
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"u3phy-utmi-apb", "u3phy-pipe-apb";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u3phy_utmi: utmi@ff470000 {
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reg = <0x0 0xff470000 0x0 0x8000>;
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#phy-cells = <0>;
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};
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u3phy_pipe: pipe@ff478000 {
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reg = <0x0 0xff478000 0x0 0x8000>;
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#phy-cells = <0>;
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};
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};
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