Hisilicon hix5hd2 gmac controller
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Required properties:
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- compatible: should contain one of the following SoC strings:
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* "hisilicon,hix5hd2-gmac"
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* "hisilicon,hi3798cv200-gmac"
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* "hisilicon,hi3516a-gmac"
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and one of the following version string:
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* "hisilicon,hisi-gmac-v1"
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* "hisilicon,hisi-gmac-v2"
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The version v1 includes SoCs hix5hd2.
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The version v2 includes SoCs hi3798cv200, hi3516a.
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- reg: specifies base physical address(s) and size of the device registers.
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The first region is the MAC register base and size.
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The second region is external interface control register.
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- interrupts: should contain the MAC interrupt.
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- #address-cells: must be <1>.
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- #size-cells: must be <0>.
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- phy-mode: see ethernet.txt [1].
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- phy-handle: see ethernet.txt [1].
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- mac-address: see ethernet.txt [1].
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- clocks: clock phandle and specifier pair.
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- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional).
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- resets: should contain the phandle to the MAC core reset signal(optional),
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the MAC interface reset signal(optional)
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and the PHY reset signal(optional).
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- reset-names: contain the reset signal name "mac_core"(optional),
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"mac_ifc"(optional) and "phy"(optional).
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- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
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The 1st cell is reset pre-delay in micro seconds.
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The 2nd cell is reset pulse in micro seconds.
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The 3rd cell is reset post-delay in micro seconds.
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- PHY subnode: inherits from phy binding [2]
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[1] Documentation/devicetree/bindings/net/ethernet.txt
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[2] Documentation/devicetree/bindings/net/phy.txt
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Example:
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gmac0: ethernet@f9840000 {
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compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
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reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;
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interrupts = <0 71 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy-mode = "rgmii";
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phy-handle = <&phy2>;
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mac-address = [00 00 00 00 00 00];
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clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
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clock-names = "mac_core", "mac_ifc";
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resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
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reset-names = "mac_core", "mac_ifc", "phy";
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hisilicon,phy-reset-delays-us = <10000 10000 30000>;
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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};
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