* Rockchip Codec Digital Interface
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Required properties:
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- compatible: should be one of the following
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- "rockchip,codec-digital-v1"
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- "rockchip,rk3568-codec-digital"
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- "rockchip,rv1126-codec-digital"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
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- clock-names: clock names.
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- rockchip,bclk-fs: configure the bclk fs.
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- resets: a list of phandle + reset-specifer paris, one for each entry in reset-names.
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- reset-names: reset names, should include "reset".
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- rockchip,grf: the phandle of the syscon node for GRF register.
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Optional properties:
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- rockchip,clk-sync-mode: This is a boolean property, if present, using clk
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sync mode.
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- rockchip,pwm-output-mode: This is a boolean property, if present, output pwm
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to drive spk.
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- rockchip,pa-ctl-delay-ms: The unsigned inter property, if present, will delay
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enable power amplifier with specified milliseconds.
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- pa-ctl-gpios: The gpio of Power Amplifier Controller.
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Example:
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rkacdc_dig: codec-digital@ff850000 {
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compatible = "rockchip,codec-digital-v1";
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reg = <0xff850000 0x1000>;
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clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>,
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<&cru PCLK_ACDCDIG>;
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clock-names = "adc", "dac", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&acodec_pins>;
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resets = <&cru SRST_ACDCDIG>;
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reset-names = "reset" ;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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