ROCKCHIP COMBO PHY WITH NANENG IP BLOCK
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Required properties (phy (parent) node):
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- compatible : should be one of the listed compatibles:
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* "rockchip,rk3568-naneng-combphy"
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- reg : the address offset of grf for combo-phy configuration.
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- rockchip,pipe-grf : phandle to the syscon managing the "pipe general register files"
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- rockchip,pipe-phy-grf: phandle to the syscon managing the "phy general register files"
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- clocks : phandle + phy specifier pair, for the input clocks of phy.
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- clock-names : input clocks name of phy.
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- resets : phandle + reset specifier pairs.
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- reset-names : reset names of phy.
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- #clock-cells : should be 1.
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Optional properties:
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- assigned-clocks : phandle of refclk.
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- assigned-clock-parents : parent of clk_xxx_osc or clk_xxx_div.
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Refer to clk/clock-bindings.txt for generic clock
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consumer properties.
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- rockchip,dis-u3otg0-port: when set, disable the u3 root port of otg0 host.
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- rockchip,dis-u3otg1-port: when set, disable the u3 root port of otg1 host.
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Example:
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combphy0: phy@fe820000 {
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compatible = "rockchip,rk3568-naneng-combphy";
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reg = <0x0 0xfe820000 0x0 0x100>;
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#phy-cells = <1>;
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clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
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clock-names = "refclk", "apbclk";
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resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
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reset-names = "combphy-apb", "combphy";
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rockchip,pipe-grf = <&pipegrf>;
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rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
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status = "disabled";
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};
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