Binding for the AXS10X Generic PLL clock
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible: should be "snps,axs10x-<name>-pll-clock"
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"snps,axs10x-arc-pll-clock"
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"snps,axs10x-pgu-pll-clock"
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- reg: should always contain 2 pairs address - length: first for PLL config
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registers and second for corresponding LOCK CGU register.
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- clocks: shall be the input parent clock phandle for the PLL.
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- #clock-cells: from common clock binding; Should always be set to 0.
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Example:
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input-clk: input-clk {
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clock-frequency = <33333333>;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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core-clk: core-clk@80 {
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compatible = "snps,axs10x-arc-pll-clock";
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reg = <0x80 0x10>, <0x100 0x10>;
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#clock-cells = <0>;
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clocks = <&input-clk>;
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};
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