/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3562.h>
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#include <asm/arch/ioc_rk3562.h>
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#include <asm/arch/rk_atags.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <asm/arch/clock.h>
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#include <dt-bindings/clock/rk3562-cru.h>
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#include <asm/arch-rockchip/rockchip_smccc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FIREWALL_DDR_BASE 0xfef00000
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#define FW_DDR_MST3_REG 0x2c /* usb */
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#define FW_DDR_MST4_REG 0x30 /* emmc */
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#define FW_DDR_MST5_REG 0x34 /* fspi */
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#define FW_DDR_MST6_REG 0x38 /* sdmmc mcu */
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#define FW_DDR_CON_REG 0x80
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#define PMU_GRF_BASE 0xff010000
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#define PMU_GRF_SOC_CON9 0x0124
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#define SYS_GRF_BASE 0xff030000
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#define SYS_GRF_SOC_CON5 0x0414
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#define SYS_GRF_SOC_CON6 0x0418
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#define PERI_GRF_BASE 0xff040000
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#define PERI_GRF_AUDIO_CON 0x0070
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#define PIPEPHY_GRF_BASE 0xff098000
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#define PIPEPHY_PIPE_CON5 0x0014
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#define TOP_CRU_BASE 0xff100000
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#define TOP_CRU_GATE_CON23 0x035c
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#define TOP_CRU_SOFTRST_CON23 0x045c
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#define TOP_CRU_CM0_GATEMASK 0x0680
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#define PMU0_CRU_BASE 0xff110000
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#define PMU1_CRU_BASE 0xff118000
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#define PMU1_CRU_GATE_CON02 0x0188
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#define PMU1_CRU_SOFTRST_CON02 0x0208
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#define PMU1_CRU_CM0_GATEMASK 0x0420
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#define PMU_BASE_ADDR 0xff258000
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#define PMU2_BIU_IDLE_SFTCON0 0x110
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#define PMU2_BIU_IDLE_ACK_STS0 0x120
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#define PMU2_BIT_IDLE_STS0 0x128
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#define PMU2_PWR_GATE_SFTCON0 0x210
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#define PMU2_PWR_GATE_STS0 0x230
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#define PMU2_MEM_SD_SFTCON0 0x300
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/* PMU2_PWR_GATE_SFTCON0 */
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#define PD_GPU_DWN_SFTENA BIT(0)
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#define PD_VI_DWN_SFTENA BIT(5)
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#define PD_VO_DWN_SFTENA BIT(6)
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/* PMU2_BIU_IDLE_SFTCON0 */
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#define IDLE_REQ_GPU_SFTENA BIT(1)
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#define IDLE_REQ_VI_SFTENA BIT(3)
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#define IDLE_REQ_VO_SFTENA BIT(4)
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/* PMU2_BIU_IDLE_ACK_STS0 */
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#define IDLE_ACK_GPU BIT(1)
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#define IDLE_ACK_VI BIT(3)
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#define IDLE_ACK_VO BIT(4)
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/* PMU2_BIT_IDLE_STS0 */
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#define IDLE_GPU BIT(1)
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#define IDLE_VI BIT(3)
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#define IDLE_VO BIT(4)
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#define CRYPTO_PRIORITY_REG 0xfeeb0108
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#define DCF_PRIORITY_REG 0xfee10408
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#define DMA2DDR_PRIORITY_REG 0xfee03808
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#define DMAC_PRIORITY_REG 0xfeeb0208
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#define EMMC_PRIORITY_REG 0xfeeb0308
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#define FSPI_PRIORITY_REG 0xfeeb0408
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#define GMAC_PRIORITY_REG 0xfee10208
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#define GPU_PRIORITY_REG 0xfee30008
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#define ISP_PRIORITY_REG 0xfee70008
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#define MAC100_PRIORITY_REG 0xfee10308
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#define MCU_PRIORITY_REG 0xfee10008
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#define PCIE_PRIORITY_REG 0xfeea0008
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#define RKDMA_PRIORITY_REG 0xfeeb0508
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#define SDMMC0_PRIORITY_REG 0xfeeb0608
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#define SDMMC1_PRIORITY_REG 0xfeeb0708
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#define USB2_PRIORITY_REG 0xfeeb0808
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#define USB3_PRIORITY_REG 0xfeea0108
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#define VICAP_PRIORITY_REG 0xfee70108
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#define VOP_PRIORITY_REG 0xfee80008
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#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region rk3562_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xfc000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xfc000000UL,
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.phys = 0xfc000000UL,
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.size = 0x04000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3562_mem_map;
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#endif
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#define GPIO0_IOC_BASE 0xFF080000
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#define GPIO1_IOC_BASE 0xFF060000
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#define GPIO1A_IOMUX_SEL_L 0x0
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#define GPIO1A_IOMUX_SEL_H 0x4
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#define GPIO1B_IOMUX_SEL_L 0x8
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#define GPIO1_IOC_GPIO1A_DS0 0x200
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#define GPIO1_IOC_GPIO1A_DS1 0x204
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#define GPIO1_IOC_GPIO1B_DS0 0x210
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#define GPIO2_IOC_BASE 0xFF060000
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#define GPIO2_IOC_IO_VSEL0 0x300
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/* GPIO2_IOC_IO_VSEL0 */
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#define POC_VCCIO2_VD_3V3 BIT(12)
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#define GPIO3_IOC_BASE 0xFF070000
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#define GPIO4_IOC_BASE 0xFF070000
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/* UART0 iomux */
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/* gpio0d0_sel */
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#define UART0_RX_M0 1
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#define UART0_RX_M0_OFFSET 0
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#define UART0_RX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
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/* gpio0d1_sel */
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#define UART0_TX_M0 1
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#define UART0_TX_M0_OFFSET 4
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#define UART0_TX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
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/* gpio1b3_sel */
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#define UART0_RX_M1 2
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#define UART0_RX_M1_OFFSET 12
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#define UART0_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
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/* gpio1b4_sel */
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#define UART0_TX_M1 2
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#define UART0_TX_M1_OFFSET 0
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#define UART0_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
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/* UART1 iomux */
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/* gpio1d1_sel */
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#define UART1_RX_M0 1
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#define UART1_RX_M0_OFFSET 4
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#define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
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/* gpio1d2_sel */
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#define UART1_TX_M0 1
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#define UART1_TX_M0_OFFSET 8
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#define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
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/* gpio4a6_sel */
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#define UART1_RX_M1 4
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#define UART1_RX_M1_OFFSET 8
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#define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
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/* gpio4a5_sel */
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#define UART1_TX_M1 4
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#define UART1_TX_M1_OFFSET 4
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#define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
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/* UART2 iomux */
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/* gpio0c1_sel */
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#define UART2_RX_M0 1
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#define UART2_RX_M0_OFFSET 4
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#define UART2_RX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
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/* gpio0c0_sel */
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#define UART2_TX_M0 1
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#define UART2_TX_M0_OFFSET 0
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#define UART2_TX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
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/* gpio3a1_sel */
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#define UART2_RX_M1 2
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#define UART2_RX_M1_OFFSET 4
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#define UART2_RX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
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/* gpio3a0_sel */
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#define UART2_TX_M1 2
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#define UART2_TX_M1_OFFSET 0
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#define UART2_TX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
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/* UART3 iomux */
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/* gpio4b5_sel */
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#define UART3_RX_M0 7
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#define UART3_RX_M0_OFFSET 4
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#define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
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/* gpio4b4_sel */
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#define UART3_TX_M0 7
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#define UART3_TX_M0_OFFSET 0
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#define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
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/* gpio3c0_sel */
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#define UART3_RX_M1 3
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#define UART3_RX_M1_OFFSET 0
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#define UART3_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
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/* gpio3b7_sel */
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#define UART3_TX_M1 3
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#define UART3_TX_M1_OFFSET 12
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#define UART3_TX_M1_ADDR (GPIO3_IOC_BASE + 0x4C)
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/* UART4 iomux */
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/* gpio3d1_sel */
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#define UART4_RX_M0 4
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#define UART4_RX_M0_OFFSET 4
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#define UART4_RX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
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/* gpio3d0_sel */
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#define UART4_TX_M0 4
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#define UART4_TX_M0_OFFSET 0
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#define UART4_TX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
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/* gpio1d5_sel */
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#define UART4_RX_M1 3
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#define UART4_RX_M1_OFFSET 4
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#define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
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/* gpio1d6_sel */
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#define UART4_TX_M1 3
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#define UART4_TX_M1_OFFSET 8
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#define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
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/* UART5 iomux */
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/* gpio1b7_sel */
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#define UART5_RX_M0 3
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#define UART5_RX_M0_OFFSET 12
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#define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0xC)
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/* gpio1c0_sel */
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#define UART5_TX_M0 3
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#define UART5_TX_M0_OFFSET 0
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#define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x10)
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/* gpio3a7_sel */
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#define UART5_RX_M1 5
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#define UART5_RX_M1_OFFSET 12
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#define UART5_RX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
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/* gpio3a6_sel */
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#define UART5_TX_M1 5
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#define UART5_TX_M1_OFFSET 8
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#define UART5_TX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
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/* UART6 iomux */
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/* gpio0c7_sel */
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#define UART6_RX_M0 1
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#define UART6_RX_M0_OFFSET 12
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#define UART6_RX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
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/* gpio0c6_sel */
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#define UART6_TX_M0 1
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#define UART6_TX_M0_OFFSET 8
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#define UART6_TX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
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/* gpio4b0_sel */
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#define UART6_RX_M1 6
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#define UART6_RX_M1_OFFSET 0
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#define UART6_RX_M1_ADDR (GPIO4_IOC_BASE + 0x68)
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/* gpio4a7_sel */
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#define UART6_TX_M1 6
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#define UART6_TX_M1_OFFSET 12
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#define UART6_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
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/* UART7 iomux */
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/* gpio3c7_sel */
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#define UART7_RX_M0 4
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#define UART7_RX_M0_OFFSET 12
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#define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
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/* gpio3c4_sel */
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#define UART7_TX_M0 4
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#define UART7_TX_M0_OFFSET 0
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#define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
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/* gpio1b3_sel */
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#define UART7_RX_M1 3
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#define UART7_RX_M1_OFFSET 12
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#define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
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/* gpio1b4_sel */
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#define UART7_TX_M1 3
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#define UART7_TX_M1_OFFSET 0
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#define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
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/* UART8 iomux */
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/* gpio3b3_sel */
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#define UART8_RX_M0 3
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#define UART8_RX_M0_OFFSET 12
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#define UART8_RX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
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/* gpio3b2_sel */
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#define UART8_TX_M0 3
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#define UART8_TX_M0_OFFSET 8
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#define UART8_TX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
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/* gpio3d5_sel */
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#define UART8_RX_M1 4
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#define UART8_RX_M1_OFFSET 4
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#define UART8_RX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
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/* gpio3d4_sel */
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#define UART8_TX_M1 4
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#define UART8_TX_M1_OFFSET 0
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#define UART8_TX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
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/* UART9 iomux */
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/* gpio4b3_sel */
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#define UART9_RX_M0 4
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#define UART9_RX_M0_OFFSET 12
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#define UART9_RX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
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/* gpio4b2_sel */
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#define UART9_TX_M0 4
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#define UART9_TX_M0_OFFSET 8
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#define UART9_TX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
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/* gpio3c3_sel */
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#define UART9_RX_M1 3
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#define UART9_RX_M1_OFFSET 12
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#define UART9_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
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/* gpio3c2_sel */
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#define UART9_TX_M1 3
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#define UART9_TX_M1_OFFSET 8
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#define UART9_TX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
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#define set_uart_iomux(bits_offset, bits_val, addr) \
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writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
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#define set_uart_iomux_rx(ID, MODE) \
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set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
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#define set_uart_iomux_tx(ID, MODE) \
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set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
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void board_debug_uart_init(void)
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{
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/* UART 0 */
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff210000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART0_M0 Switch iomux */
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set_uart_iomux_rx(0, 0);
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set_uart_iomux_tx(0, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART0_M1 Switch iomux */
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set_uart_iomux_rx(0, 1);
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set_uart_iomux_tx(0, 1);
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#endif
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/* UART 1 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff670000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART1_M0 Switch iomux */
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set_uart_iomux_rx(1, 0);
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set_uart_iomux_tx(1, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART1_M1 Switch iomux */
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set_uart_iomux_rx(1, 1);
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set_uart_iomux_tx(1, 1);
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#endif
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/* UART 2 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff680000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART2_M0 Switch iomux */
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set_uart_iomux_rx(2, 0);
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set_uart_iomux_tx(2, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART2_M1 Switch iomux */
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set_uart_iomux_rx(2, 1);
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set_uart_iomux_tx(2, 1);
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#endif
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/* UART 3 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART3_M0 Switch iomux */
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set_uart_iomux_rx(3, 0);
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set_uart_iomux_tx(3, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART3_M1 Switch iomux */
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set_uart_iomux_rx(3, 1);
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set_uart_iomux_tx(3, 1);
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#endif
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/* UART 4 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6a0000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART4_M0 Switch iomux */
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set_uart_iomux_rx(4, 0);
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set_uart_iomux_tx(4, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART4_M1 Switch iomux */
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set_uart_iomux_rx(4, 1);
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set_uart_iomux_tx(4, 1);
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#endif
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/* UART 5 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6b0000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART5_M0 Switch iomux */
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set_uart_iomux_rx(5, 0);
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set_uart_iomux_tx(5, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART5_M1 Switch iomux */
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set_uart_iomux_rx(5, 1);
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set_uart_iomux_tx(5, 1);
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#endif
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/* UART 6 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6c0000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART6_M0 Switch iomux */
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set_uart_iomux_rx(6, 0);
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set_uart_iomux_tx(6, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART6_M1 Switch iomux */
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set_uart_iomux_rx(6, 1);
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set_uart_iomux_tx(6, 1);
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#endif
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/* UART 7 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6d0000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART7_M0 Switch iomux */
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set_uart_iomux_rx(7, 0);
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set_uart_iomux_tx(7, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART7_M1 Switch iomux */
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set_uart_iomux_rx(7, 1);
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set_uart_iomux_tx(7, 1);
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#endif
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/* UART 8 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6e0000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
|
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/* UART8_M0 Switch iomux */
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set_uart_iomux_rx(8, 0);
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set_uart_iomux_tx(8, 0);
|
#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
|
(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
|
|
/* UART8_M1 Switch iomux */
|
set_uart_iomux_rx(8, 1);
|
set_uart_iomux_tx(8, 1);
|
#endif
|
/* UART 9 */
|
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6f0000)
|
#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
|
(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
|
|
/* UART9_M0 Switch iomux */
|
set_uart_iomux_rx(9, 0);
|
set_uart_iomux_tx(9, 0);
|
#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
|
(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
|
|
/* UART9_M1 Switch iomux */
|
set_uart_iomux_rx(9, 1);
|
set_uart_iomux_tx(9, 1);
|
#endif
|
#endif
|
}
|
|
int fit_standalone_release(char *id, uintptr_t entry_point)
|
{
|
/* bus m0 configuration: */
|
/* open hclk_dcache / hclk_icache / clk_bus m0 rtc / fclk_bus_m0_core */
|
writel(0x03180000, TOP_CRU_BASE + TOP_CRU_GATE_CON23);
|
|
/* open bus m0 sclk / bus m0 hclk / bus m0 dclk */
|
writel(0x00070000, TOP_CRU_BASE + TOP_CRU_CM0_GATEMASK);
|
|
/* mcu_cache_peripheral_addr */
|
writel(0xa0000000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);
|
writel(0xffb40000, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
|
|
sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
|
ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
|
0xffff0000 | (entry_point >> 16));
|
sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
|
ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR, 0xffffa000);
|
|
/* release dcache / icache / bus m0 jtag / bus m0 */
|
writel(0x03280000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON23);
|
|
/* release pmu m0 jtag / pmu m0 */
|
/* writel(0x00050000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON02); */
|
|
return 0;
|
}
|
|
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
|
static void qos_priority_init(void)
|
{
|
u32 delay;
|
u32 i;
|
|
/* power up vo,vi,gpu */
|
rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0,
|
PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA);
|
delay = 1000;
|
do {
|
udelay(1);
|
delay--;
|
if (delay == 0) {
|
printf("Fail to set domain. PMU2_PWR_GATE_STS0=0x%x\n",
|
readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0));
|
hang();
|
}
|
} while (readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0) &
|
(PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA));
|
/* power up vop memory */
|
for (i = 0; i < 16; i++)
|
rk_clrreg(PMU_BASE_ADDR + PMU2_MEM_SD_SFTCON0, BIT(i));
|
|
/* release vo,vi,gpu idle request */
|
rk_clrreg(PMU_BASE_ADDR + PMU2_BIU_IDLE_SFTCON0,
|
(IDLE_REQ_VO_SFTENA | IDLE_REQ_VI_SFTENA));
|
|
delay = 1000;
|
/* wait ack status */
|
do {
|
udelay(1);
|
delay--;
|
if (delay == 0) {
|
printf("Fail to get ack on domain. PMU2_BIU_IDLE_ACK_STS0=0x%x\n",
|
readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0));
|
hang();
|
}
|
} while (readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0) &
|
(IDLE_ACK_VO | IDLE_ACK_VI));
|
|
delay = 1000;
|
/* wait idle status */
|
do {
|
udelay(1);
|
delay--;
|
if (delay == 0) {
|
printf("Fail to set idle on domain. PMU2_BIT_IDLE_STS0=0x%x\n",
|
readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0));
|
hang();
|
}
|
} while (readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0) &
|
(IDLE_VO | IDLE_VI));
|
|
/*
|
* modify default qos priority setting, then
|
* Peri > VOP/ISP/VICAP > CPU > GPU/NPU/RKVDEC/RGA/Other
|
* (5) (4) (3) (2)
|
*
|
* NOTE: GPU qos init is in kernel, in case that vdd gpu is off now.
|
*/
|
writel(QOS_PRIORITY_LEVEL(5, 5), CRYPTO_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), DMAC_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), EMMC_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), FSPI_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), GMAC_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), MAC100_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), MCU_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), RKDMA_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC0_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC1_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), USB2_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(5, 5), USB3_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(4, 4), ISP_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(4, 4), VICAP_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(4, 4), VOP_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(2, 2), DCF_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(2, 2), DMA2DDR_PRIORITY_REG);
|
writel(QOS_PRIORITY_LEVEL(2, 2), PCIE_PRIORITY_REG);
|
}
|
|
int arch_cpu_init(void)
|
{
|
u32 val;
|
|
/* Set the emmc to access ddr memory */
|
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
|
writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
|
|
/* Set the sdmmc to access ddr memory */
|
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
|
writel(val & 0xff0000ff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
|
|
/*
|
* Set SAIx_MCLK as input default
|
*
|
* It's safe to set mclk as input default to avoid high freq glitch
|
* which may make devices work unexpected. And then enabled by
|
* kernel stage or any state where user use it.
|
*/
|
writel(0x0a100000, PERI_GRF_BASE + PERI_GRF_AUDIO_CON);
|
|
/* Assert reset the pipe phy to save power and de-assert when in use */
|
writel(0x00030001, PIPEPHY_GRF_BASE + PIPEPHY_PIPE_CON5);
|
|
#if defined(CONFIG_ROCKCHIP_SFC)
|
/* Set the fspi to access ddr memory */
|
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
|
writel(val & 0x00ffffff, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
|
|
/*
|
* Fix fspi io ds level:
|
*
|
* level 2 for 1V8
|
* level 3 for 3V3
|
*/
|
if (readl(GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L) == 0x2222) {
|
if (readl(GPIO2_IOC_BASE + GPIO2_IOC_IO_VSEL0) & POC_VCCIO2_VD_3V3) {
|
writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
|
writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
|
writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
|
} else {
|
writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
|
writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
|
writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
|
}
|
}
|
#endif
|
|
qos_priority_init();
|
|
return 0;
|
}
|
#endif
|
