/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3528.h>
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#include <asm/arch/ioc_rk3528.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FIREWALL_DDR_BASE 0xff2e0000
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#define FW_DDR_MST1_REG 0x44
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#define FW_DDR_MST6_REG 0x58
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#define FW_DDR_MST7_REG 0x5c
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#define FW_DDR_MST11_REG 0x6c
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#define FW_DDR_MST14_REG 0x78
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#define FW_DDR_MST16_REG 0x80
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#define FW_DDR_MST_REG 0xf0
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#define VENC_GRF_BASE 0xff320000
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#define VENC_GRF_CON1 0x4
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#define VPU_GRF_BASE 0xff340000
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#define VPU_GRF_CON4 0x14
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#define PMU_SGRF_BASE 0xff440000
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#define PMU_SGRF_SOC_CON4 0x10
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#define PMU_SGRF_SOC_CON5 0x14
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#define PMU_SGRF_SOC_CON6 0x18
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#define PMU_SGRF_SOC_CON8 0x20
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#define PMU_SGRF_SOC_CON11 0x2c
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#define PMU_CRU_BASE 0xff4b0000
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#define PMU_CRU_GATE_CON00 0x800
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#define PMU_CRU_SOFTRST_CON00 0xa00
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#define GPIO1C_IOMUX_SEL_H 0x034
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#define GPIO1D_IOMUX_SEL_L 0x038
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#define GPIO1D_IOMUX_SEL_H 0x03c
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#define CPU_PRIORITY_REG 0xff210008
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#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region rk3528_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xfc000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xfc000000UL,
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.phys = 0xfc000000UL,
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.size = 0x04000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3528_mem_map;
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#endif
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#define GPIO0_IOC_BASE 0xFF540000
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#define GPIO1_IOC_BASE 0xFF560000
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#define GPIO2_IOC_BASE 0xFF570000
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#define GPIO3_IOC_BASE 0xFF560000
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#define GPIO4_IOC_BASE 0xFF550000
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#define GPIO1_IOC_GPIO1D_IOMUX_SEL_L (GPIO1_IOC_BASE + 0x38)
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#define GPIO1_IOC_GPIO1C_DS_2 (GPIO1_IOC_BASE + 0x148)
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#define GPIO1_IOC_GPIO1C_DS_3 (GPIO1_IOC_BASE + 0x14C)
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#define GPIO1_IOC_GPIO1D_DS_0 (GPIO1_IOC_BASE + 0x150)
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#define GPIO1_IOC_GPIO1D_DS_1 (GPIO1_IOC_BASE + 0x154)
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#define GPIO1_IOC_GPIO1D_DS_2 (GPIO1_IOC_BASE + 0x158)
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/* uart0 iomux */
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/* gpio4c7 */
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#define UART0_RX_M0 1
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#define UART0_RX_M0_OFFSET 12
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#define UART0_RX_M0_ADDR (GPIO4_IOC_BASE + 0x94)
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/* gpio4d0 */
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#define UART0_TX_M0 1
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#define UART0_TX_M0_OFFSET 0
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#define UART0_TX_M0_ADDR (GPIO4_IOC_BASE + 0x98)
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/* gpio2a0 */
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#define UART0_RX_M1 2
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#define UART0_RX_M1_OFFSET 0
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#define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
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/* gpio2a1 */
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#define UART0_TX_M1 2
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#define UART0_TX_M1_OFFSET 4
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#define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
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/* uart1 iomux */
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/* gpio4a7 */
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#define UART1_RX_M0 2
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#define UART1_RX_M0_OFFSET 12
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#define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
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/* gpio4a6 */
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#define UART1_TX_M0 2
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#define UART1_TX_M0_OFFSET 8
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#define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
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/* gpio4c6 */
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#define UART1_RX_M1 2
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#define UART1_RX_M1_OFFSET 8
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#define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
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/* gpio4c5 */
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#define UART1_TX_M1 2
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#define UART1_TX_M1_OFFSET 4
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#define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
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/* uart2 iomux */
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/* gpio3a0 */
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#define UART2_RX_M0 1
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#define UART2_RX_M0_OFFSET 0
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#define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
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/* gpio3a1 */
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#define UART2_TX_M0 1
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#define UART2_TX_M0_OFFSET 4
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#define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
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/* gpio1b0 */
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#define UART2_RX_M1 1
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#define UART2_RX_M1_OFFSET 0
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#define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
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/* gpio1b1 */
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#define UART2_TX_M1 1
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#define UART2_TX_M1_OFFSET 4
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#define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
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/* uart3 iomux */
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/* gpio4b0 */
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#define UART3_RX_M0 2
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#define UART3_RX_M0_OFFSET 0
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#define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
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/* gpio4b1 */
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#define UART3_TX_M0 2
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#define UART3_TX_M0_OFFSET 4
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#define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
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/* gpio4b7 */
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#define UART3_RX_M1 3
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#define UART3_RX_M1_OFFSET 12
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#define UART3_RX_M1_ADDR (GPIO4_IOC_BASE + 0x8C)
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/* gpio4c0 */
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#define UART3_TX_M1 3
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#define UART3_TX_M1_OFFSET 0
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#define UART3_TX_M1_ADDR (GPIO4_IOC_BASE + 0x90)
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/* uart4 iomux */
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/* gpio2a2 */
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#define UART4_RX_M0 3
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#define UART4_RX_M0_OFFSET 8
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#define UART4_RX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
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/* gpio2a3 */
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#define UART4_TX_M0 3
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#define UART4_TX_M0_OFFSET 12
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#define UART4_TX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
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/* uart5 iomux */
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/* gpio1a2 */
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#define UART5_RX_M0 2
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#define UART5_RX_M0_OFFSET 8
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#define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
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/* gpio1a3 */
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#define UART5_TX_M0 2
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#define UART5_TX_M0_OFFSET 12
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#define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
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/* gpio1d4 */
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#define UART5_RX_M1 2
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#define UART5_RX_M1_OFFSET 0
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#define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
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/* gpio1d7 */
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#define UART5_TX_M1 2
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#define UART5_TX_M1_OFFSET 12
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#define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
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/* uart6 iomux */
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/* gpio3a7 */
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#define UART6_RX_M0 4
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#define UART6_RX_M0_OFFSET 12
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#define UART6_RX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
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/* gpio3a6 */
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#define UART6_TX_M0 4
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#define UART6_TX_M0_OFFSET 8
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#define UART6_TX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
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/* gpio3c3 */
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#define UART6_RX_M1 4
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#define UART6_RX_M1_OFFSET 12
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#define UART6_RX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
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/* gpio3c1 */
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#define UART6_TX_M1 4
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#define UART6_TX_M1_OFFSET 4
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#define UART6_TX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
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/* uart7 iomux */
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/* gpio3b3 */
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#define UART7_RX_M0 4
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#define UART7_RX_M0_OFFSET 12
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#define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
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/* gpio3b2 */
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#define UART7_TX_M0 4
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#define UART7_TX_M0_OFFSET 8
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#define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
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/* gpio1b3 */
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#define UART7_RX_M1 4
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#define UART7_RX_M1_OFFSET 12
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#define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
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/* gpio1b2 */
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#define UART7_TX_M1 4
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#define UART7_TX_M1_OFFSET 8
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#define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
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#define set_uart_iomux(bits_offset, bits_val, addr) \
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writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
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#define set_uart_iomux_rx(ID, MODE) \
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set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
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#define set_uart_iomux_tx(ID, MODE) \
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set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
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void board_debug_uart_init(void)
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{
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/* UART 0 */
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f0000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART0_M0 Switch iomux */
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set_uart_iomux_rx(0, 0);
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set_uart_iomux_tx(0, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART0_M1 Switch iomux */
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set_uart_iomux_rx(0, 1);
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set_uart_iomux_tx(0, 1);
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#endif
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/* UART 1 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f8000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART1_M0 Switch iomux */
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set_uart_iomux_rx(1, 0);
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set_uart_iomux_tx(1, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART1_M1 Switch iomux */
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set_uart_iomux_rx(1, 1);
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set_uart_iomux_tx(1, 1);
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#endif
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/* UART 2 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa00000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART2_M0 Switch iomux */
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set_uart_iomux_rx(2, 0);
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set_uart_iomux_tx(2, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART2_M1 Switch iomux */
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set_uart_iomux_rx(2, 1);
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set_uart_iomux_tx(2, 1);
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#endif
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/* UART 3 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa08000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART3_M0 Switch iomux */
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set_uart_iomux_rx(3, 0);
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set_uart_iomux_tx(3, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART3_M1 Switch iomux */
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set_uart_iomux_rx(3, 1);
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set_uart_iomux_tx(3, 1);
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#endif
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/* UART 4 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa10000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART4_M0 Switch iomux */
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set_uart_iomux_rx(4, 0);
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set_uart_iomux_tx(4, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART4_M1 Switch iomux */
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set_uart_iomux_rx(4, 1);
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set_uart_iomux_tx(4, 1);
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#endif
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/* UART 5 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa18000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART5_M0 Switch iomux */
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set_uart_iomux_rx(5, 0);
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set_uart_iomux_tx(5, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART5_M1 Switch iomux */
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set_uart_iomux_rx(5, 1);
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set_uart_iomux_tx(5, 1);
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#endif
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/* UART 6 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa20000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART6_M0 Switch iomux */
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set_uart_iomux_rx(6, 0);
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set_uart_iomux_tx(6, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART6_M1 Switch iomux */
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set_uart_iomux_rx(6, 1);
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set_uart_iomux_tx(6, 1);
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#endif
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/* UART 7 */
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa28000)
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#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
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/* UART7_M0 Switch iomux */
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set_uart_iomux_rx(7, 0);
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set_uart_iomux_tx(7, 0);
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#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
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(CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
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/* UART7_M1 Switch iomux */
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set_uart_iomux_rx(7, 1);
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set_uart_iomux_tx(7, 1);
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#endif
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#endif
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}
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#ifdef CONFIG_SPL_BUILD
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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if (reg & 0x1)
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return;
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asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
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dsb();
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writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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}
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#endif
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int arch_cpu_init(void)
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{
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#if defined(CONFIG_SPL_BUILD)
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u32 val;
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/*
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* Select clk_tx source as default for i2s2/i2s3
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* Set I2Sx_MCLK as input default
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*
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* It's safe to set mclk as input default to avoid high freq glitch
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* which may make devices work unexpected. And then enabled by
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* kernel stage or any state where user use it.
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*/
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writel(0x00020002, VPU_GRF_BASE + VPU_GRF_CON4);
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writel(0x40004000, VENC_GRF_BASE + VENC_GRF_CON1);
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/* Set the emmc to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
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writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
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/* Set the sdmmc to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
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writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
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/* Set the crypto to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
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writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
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#if defined(CONFIG_ROCKCHIP_SFC)
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/* Set the fspi to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
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writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
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#endif
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#ifndef CONFIG_TPL_BUILD
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/* Set cpu qos priority, then
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* Peri > VOP > CPU = RKVDEC/RKVENC/VPU > GPU/RGA/Other
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*/
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writel(QOS_PRIORITY_LEVEL(2, 2), CPU_PRIORITY_REG);
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#endif
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if (readl(GPIO1_IOC_GPIO1D_IOMUX_SEL_L) == 0x1111) {
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/*
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* set the emmc io drive strength:
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* data and cmd: level 3
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* clock: level 5
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*/
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writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_2);
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writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_3);
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writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_0);
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writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_1);
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writel(0x3F3F3F0F, GPIO1_IOC_GPIO1D_DS_2);
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}
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#elif defined(CONFIG_SUPPORT_USBPLUG)
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u32 val;
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/* Set the usb to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
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writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
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/* Set the emmc to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
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writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
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/* Set emmc iomux */
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writel(0xffff1111, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
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writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
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writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
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#if defined(CONFIG_ROCKCHIP_SFC)
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/* Set the fspi to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
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writel(val & 0xFFFF0000uL, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
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/* Set fspi iomux */
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writel(0xffff2222, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
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writel(0x000f0002, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
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writel(0x00f00020, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
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#endif
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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int spl_fit_standalone_release(char *id, uintptr_t entry_point)
|
{
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u32 val;
|
|
/* open clk_pmu_mcu_jtag / clk_mcu_32k_en / fclk_mcu_en */
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writel(0x05800000, PMU_CRU_BASE + PMU_CRU_GATE_CON00);
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/* set the mcu to access ddr memory */
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val = readl(FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
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writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
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/* writel(0x00000000, FIREWALL_DDR_BASE + FW_DDR_MST_REG); */
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/* set the mcu to secure */
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writel(0x00200000, PMU_SGRF_BASE + PMU_SGRF_SOC_CON4);
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/* open mcu_debug_en / mcu_dclk_en / mcu_hclk_en / mcu_sclk_en */
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writel(0x000f000f, PMU_SGRF_BASE + PMU_SGRF_SOC_CON5);
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/* set start addr, mcu_code_addr_start */
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writel(0xffff0000 | (entry_point >> 16), PMU_SGRF_BASE + PMU_SGRF_SOC_CON6);
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/* mcu_tcm_addr_start, multiplex pmu sram address */
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writel(0xffffff10, PMU_SGRF_BASE + PMU_SGRF_SOC_CON11);
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/* jtag_mcu_m0 gpio2a4/gpio2a5 iomux */
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/* writel(0x00ff0022, GPIO2_IOC_BASE + 0x44); */
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/* release the mcu */
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writel(0x00800000, PMU_CRU_BASE + PMU_CRU_SOFTRST_CON00);
|
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return 0;
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}
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#endif
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