/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <asm/fsl_i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pci_region pci1_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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};
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/*
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* pci_init_board()
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*
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* NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
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* per TQM834x design physical connections to external devices (PCI sockets)
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* are routed only to the PCI1 we do not account for the second one - this code
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* supports PCI1 module only. Should support for the PCI2 be required in the
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* future it needs a separate pci_controller structure (above) and handling -
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* please refer to other boards' implementation for dual PCI host controllers,
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* for example board/Marvell/db64360/pci.c, pci_init_board()
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*
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*/
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void
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pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci1_regions };
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u32 reg32;
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT
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*
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* WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
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* line actually used for clocking all external PCI devices in TQM83xx.
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* Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
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* unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
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* are known to hang the board; this issue is under investigation
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* (13 oct 05)
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*/
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reg32 = OCCR_PCICOE1;
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#if 0
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/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
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reg32 = 0xff000000;
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#endif
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if (clk->spmr & SPMR_CKID) {
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/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
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* fields accordingly */
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reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
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reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
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| OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
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| OCCR_PCICD6 | OCCR_PCICD7);
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}
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clk->occr = reg32;
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
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udelay(2000);
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mpc83xx_pci_init(1, reg);
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}
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