/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/cru_rk3288.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/pmu_rk3288.h>
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#include <asm/arch/qos_rk3288.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <power/regulator.h>
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#define GRF_BASE 0xff770000
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#define VIO0_VOP_QOS_BASE 0xffad0408
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#define VIO1_VOP_QOS_BASE 0xffad0008
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#define BUS_MSCH0_QOS_BASE 0xffac0014
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#define BUS_MSCH1_QOS_BASE 0xffac0094
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#define READLATENCY_VAL 0x34
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#define CRU_CLKSEL_CON28 0Xff7600d0
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#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
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((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
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};
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#ifndef CONFIG_TPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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static void configure_l2ctlr(void)
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{
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uint32_t l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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#ifdef CONFIG_SPL_BUILD
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configure_l2ctlr();
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#else
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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/* Use rkpwm by default */
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rk_setreg(&grf->soc_con2, 1 << 0);
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/* Disable LVDS phy */
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rk_setreg(&grf->soc_con7, 1 << 15);
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/* Select EDP clock source 24M */
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rk_setreg(CRU_CLKSEL_CON28, 1 << 15);
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/* Read latency configure */
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writel(READLATENCY_VAL, BUS_MSCH0_QOS_BASE);
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writel(READLATENCY_VAL, BUS_MSCH1_QOS_BASE);
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/* Set vop qos to highest priority */
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writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2), VIO0_VOP_QOS_BASE);
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writel(CPU_AXI_QOS_PRIORITY_LEVEL(2, 2), VIO1_VOP_QOS_BASE);
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#endif
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return 0;
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}
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#endif
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void board_debug_uart_init(void)
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{
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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}
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#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
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#ifdef CONFIG_SPL_MMC_SUPPORT
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static int configure_emmc(void)
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{
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#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
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struct gpio_desc desc;
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int ret;
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struct udevice *pinctrl;
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pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
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/*
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* TODO(sjg@chromium.org): Pick this up from device tree or perhaps
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* use the EMMC_PWREN setting.
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*/
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ret = dm_gpio_lookup_name("D9", &desc);
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if (ret) {
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debug("gpio ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_request(&desc, "emmc_pwren");
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if (ret) {
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debug("gpio_request ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
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if (ret) {
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debug("gpio dir ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_set_value(&desc, 1);
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if (ret) {
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debug("gpio value ret=%d\n", ret);
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return ret;
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}
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#endif
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return 0;
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}
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int rk_spl_board_init(void)
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{
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struct udevice *pinctrl;
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int ret = 0;
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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goto err;
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}
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/* TODO: we may need to check boot device first */
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#ifdef CONFIG_SPL_MMC_SUPPORT
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
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if (ret) {
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debug("%s: Failed to set up SD card\n", __func__);
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goto err;
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}
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#endif
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ret = configure_emmc();
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if (ret) {
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debug("%s: Failed to set up eMMC\n", __func__);
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}
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err:
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return ret;
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}
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#endif
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#endif
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int rk3288_qos_init(void)
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{
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int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
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/* set vop qos to higher priority */
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writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
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if (!fdt_node_check_compatible(gd->fdt_blob, 0,
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"rockchip,rk3288-tinker"))
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{
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/* set isp qos to higher priority */
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
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writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
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}
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return 0;
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}
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static void rk3288_detect_reset_reason(void)
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{
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struct rk3288_cru *cru = rockchip_get_cru();
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const char *reason;
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if (IS_ERR(cru))
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return;
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switch (cru->cru_glb_rst_st) {
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case GLB_POR_RST:
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reason = "POR";
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break;
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case FST_GLB_RST_ST:
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case SND_GLB_RST_ST:
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reason = "RST";
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break;
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case FST_GLB_TSADC_RST_ST:
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case SND_GLB_TSADC_RST_ST:
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reason = "THERMAL";
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break;
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case FST_GLB_WDT_RST_ST:
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case SND_GLB_WDT_RST_ST:
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reason = "WDOG";
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break;
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default:
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reason = "unknown reset";
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}
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env_set("reset_reason", reason);
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/*
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* Clear cru_glb_rst_st, so we can determine the last reset cause
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* for following resets.
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*/
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rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
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}
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__weak int rk3288_board_late_init(void)
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{
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return 0;
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}
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int rk_board_late_init(void)
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{
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rk3288_qos_init();
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rk3288_detect_reset_reason();
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return rk3288_board_late_init();
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}
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#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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static int veyron_init(void)
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{
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struct udevice *dev;
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struct clk clk;
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int ret;
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ret = regulator_get_by_platname("vdd_arm", &dev);
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if (ret) {
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debug("Cannot set regulator name\n");
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return ret;
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}
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/* Slowly raise to max CPU voltage to prevent overshoot */
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ret = regulator_set_value(dev, 1200000);
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if (ret)
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return ret;
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udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
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ret = regulator_set_value(dev, 1400000);
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if (ret)
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return ret;
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udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
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ret = rockchip_get_clk(&clk.dev);
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if (ret)
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return ret;
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clk.id = PLL_APLL;
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ret = clk_set_rate(&clk, 1800000000);
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if (IS_ERR_VALUE(ret))
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return ret;
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return 0;
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}
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int rk_board_init(void)
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{
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int ret;
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/* We do some SoC one time setting here */
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if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
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ret = veyron_init();
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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static const struct {
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char *name;
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int id;
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} clks[] = {
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{ "osc", CLK_OSC },
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{ "apll", CLK_ARM },
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{ "dpll", CLK_DDR },
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{ "cpll", CLK_CODEC },
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{ "gpll", CLK_GENERAL },
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#ifdef CONFIG_ROCKCHIP_RK3036
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{ "mpll", CLK_NEW },
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#else
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{ "npll", CLK_NEW },
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#endif
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};
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int ret, i;
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struct udevice *dev;
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ret = rockchip_get_clk(&dev);
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if (ret) {
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printf("clk-uclass not found\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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struct clk clk;
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ulong rate;
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clk.id = clks[i].id;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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continue;
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rate = clk_get_rate(&clk);
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printf("%s: %lu\n", clks[i].name, rate);
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clk_free(&clk);
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}
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return 0;
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}
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U_BOOT_CMD(
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clock, 2, 1, do_clock,
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"display information about clocks",
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""
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);
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#define GRF_SOC_CON2 0xff77024c
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int board_early_init_f(void)
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{
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struct udevice *pinctrl;
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struct udevice *dev;
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int ret;
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/*
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* This init is done in SPL, but when chain-loading U-Boot SPL will
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* have been skipped. Allow the clock driver to check if it needs
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* setting up.
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*/
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ret = rockchip_get_clk(&dev);
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if (ret) {
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debug("CLK init failed: %d\n", ret);
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return ret;
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}
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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return ret;
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}
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/* Enable debug UART */
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
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if (ret) {
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debug("%s: Failed to set up console UART\n", __func__);
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return ret;
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}
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rk_setreg(GRF_SOC_CON2, 1 << 0);
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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int rk_board_fdt_fixup(void *blob)
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{
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/* RK3288: Recognize RK3288W by HDMI Revision ID is 0x1A; */
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if (soc_is_rk3288w()) {
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if (fdt_setprop_string(blob, 0,
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"compatible", "rockchip,rk3288w"))
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printf("RK3288w set compatible failed!\n");
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}
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return 0;
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}
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#endif
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