/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk322x.h>
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#define GRF_BASE 0x11000000
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#define CRU_MISC_CON 0x110e0134
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#define SGRF_DDR_CON0 0x10150000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
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};
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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static struct rk322x_grf * const grf = (void *)GRF_BASE;
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/* We do some SoC one time setting here. */
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#ifdef CONFIG_SPL_BUILD
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/* Disable the ddr secure region setting to make it non-secure */
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rk_clrreg(SGRF_DDR_CON0, 0x4000);
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#endif
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/* PWMs select rkpwm clock source */
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rk_setreg(&grf->soc_con[2], 1 << 0);
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/* PWM0~3 io select */
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rk_setreg(&grf->con_iomux, 0xf << 0);
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/* UART1~2 io select */
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rk_setreg(&grf->con_iomux, (1 << 11) | (1 << 8));
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/* HDMI phy clock source select HDMIPHY clock out */
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rk_clrreg(CRU_MISC_CON, 1 << 13);
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/*
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* The integrated macphy is enabled by default, disable it
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* for saving power consuming.
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*/
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rk_clrsetreg(&grf->macphy_con[0], MACPHY_CFG_ENABLE_MASK,
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0 << MACPHY_CFG_ENABLE_SHIFT);
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/* TODO: ECO version */
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return 0;
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}
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#endif
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void board_debug_uart_init(void)
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{
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static struct rk322x_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
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GPIO1B2_GPIO = 0,
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GPIO1B2_UART21_SIN = 2,
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART1_SOUT,
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GPIO1B1_UART21_SOUT,
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};
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enum {
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CON_IOMUX_UART2SEL_SHIFT= 8,
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CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
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CON_IOMUX_UART2SEL_2 = 0,
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CON_IOMUX_UART2SEL_21,
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};
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/* Enable early UART2 channel 1 on the RK322x */
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK | GPIO1B2_MASK,
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GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
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GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->con_iomux,
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CON_IOMUX_UART2SEL_MASK,
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CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
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}
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