/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/arch/cru_px30.h>
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#include <asm/arch/grf_px30.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/uart.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/cru_px30.h>
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#include <dt-bindings/clock/px30-cru.h>
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#define PMU_PWRDN_CON 0xff000018
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#define GRF_CPU_CON1 0xff140504
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#define USBPHY_GRF_BASE 0xff2c0000
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#define VIDEO_PHY_BASE 0xff2e0000
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#define FW_DDR_CON_REG 0xff534040
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#define SERVICE_CORE_ADDR 0xff508000
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#define QOS_PRIORITY 0x08
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#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region px30_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xff000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xff000000UL,
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.phys = 0xff000000UL,
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.size = 0x01000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = px30_mem_map;
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#endif
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#define PMU_PWRDN_CON 0xff000018
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#define GRF_BASE 0xff140000
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#define CRU_BASE 0xff2b0000
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#define VIDEO_PHY_BASE 0xff2e0000
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#define SERVICE_CORE_ADDR 0xff508000
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#define DDR_FW_BASE 0xff534000
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#define FW_DDR_CON 0x40
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#define QOS_PRIORITY 0x08
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#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
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#define GRF_GPIO1A_DS2 0x0090
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#define GRF_GPIO1B_DS2 0x0094
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#define GRF_GPIO1A_E 0x00F0
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#define GRF_GPIO1B_E 0x00F4
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/* GRF_GPIO1CL_IOMUX */
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enum {
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GPIO1C1_SHIFT = 4,
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GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT,
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GPIO1C1_GPIO = 0,
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GPIO1C1_UART1_TX,
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GPIO1C0_SHIFT = 0,
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GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT,
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GPIO1C0_GPIO = 0,
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GPIO1C0_UART1_RX,
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};
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/* GRF_GPIO1DL_IOMUX */
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enum {
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GPIO1D3_SHIFT = 12,
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GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT,
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GPIO1D3_GPIO = 0,
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GPIO1D3_SDMMC_D1,
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GPIO1D3_UART2_RXM0,
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GPIO1D2_SHIFT = 8,
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GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT,
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GPIO1D2_GPIO = 0,
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GPIO1D2_SDMMC_D0,
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GPIO1D2_UART2_TXM0,
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};
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/* GRF_GPIO1DH_IOMUX */
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enum {
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GPIO1D7_SHIFT = 12,
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GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT,
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GPIO1D7_GPIO = 0,
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GPIO1D7_SDMMC_CMD,
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GPIO1D6_SHIFT = 8,
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GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT,
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GPIO1D6_GPIO = 0,
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GPIO1D6_SDMMC_CLK,
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GPIO1D5_SHIFT = 4,
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GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT,
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GPIO1D5_GPIO = 0,
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GPIO1D5_SDMMC_D3,
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GPIO1D4_SHIFT = 0,
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GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT,
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GPIO1D4_GPIO = 0,
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GPIO1D4_SDMMC_D2,
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};
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/* GRF_GPIO2BH_IOMUX */
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enum {
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GPIO2B6_SHIFT = 8,
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GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT,
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GPIO2B6_GPIO = 0,
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GPIO2B6_CIF_D1M0,
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GPIO2B6_UART2_RXM1,
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GPIO2B4_SHIFT = 0,
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GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT,
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GPIO2B4_GPIO = 0,
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GPIO2B4_CIF_D0M0,
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GPIO2B4_UART2_TXM1,
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};
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/* GRF_GPIO3AL_IOMUX */
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enum {
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GPIO3A2_SHIFT = 8,
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GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT,
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GPIO3A2_GPIO = 0,
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GPIO3A2_UART5_TX = 4,
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GPIO3A1_SHIFT = 4,
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GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT,
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GPIO3A1_GPIO = 0,
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GPIO3A1_UART5_RX = 4,
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};
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enum {
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IOVSEL6_CTRL_SHIFT = 0,
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IOVSEL6_CTRL_MASK = BIT(0),
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VCCIO6_SEL_BY_GPIO = 0,
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VCCIO6_SEL_BY_IOVSEL6,
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IOVSEL6_SHIFT = 1,
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IOVSEL6_MASK = BIT(1),
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VCCIO6_3V3 = 0,
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VCCIO6_1V8,
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};
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/*
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* The voltage of VCCIO6(which is the voltage domain of emmc/flash/sfc
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* interface) can indicated by GPIO0_B6 or io_vsel6. The SOC defaults
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* use GPIO0_B6 to indicate power supply voltage for VCCIO6 by hardware,
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* then we can switch to io_vsel6 after system power on, and release GPIO0_B6
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* for other usage.
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*/
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#define GPIO0_B6 14
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#define GPIO0_BASE 0xff040000
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#define GPIO_SWPORTA_DDR 0x4
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#define GPIO_EXT_PORTA 0x50
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static int grf_vccio6_vsel_init(void)
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{
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static struct px30_grf * const grf = (void *)GRF_BASE;
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u32 val;
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val = readl(GPIO0_BASE + GPIO_SWPORTA_DDR);
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val &= ~BIT(GPIO0_B6);
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writel(val, GPIO0_BASE + GPIO_SWPORTA_DDR);
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if (readl(GPIO0_BASE + GPIO_EXT_PORTA) & BIT(GPIO0_B6))
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val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT |
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VCCIO6_1V8 << IOVSEL6_SHIFT;
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else
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val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT |
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VCCIO6_3V3 << IOVSEL6_SHIFT;
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rk_clrsetreg(&grf->io_vsel, IOVSEL6_CTRL_MASK | IOVSEL6_MASK, val);
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return 0;
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}
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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/* We do some SoC one time setting here. */
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/* Disable the ddr secure region setting to make it non-secure */
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writel(0x0, FW_DDR_CON_REG);
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if (soc_is_px30s()) {
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/* set the emmc data(GPIO1A0-A7) drive strength to 14.2ma */
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writel(0xFFFF0000, GRF_BASE + GRF_GPIO1A_DS2);
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writel(0xFFFFFFFF, GRF_BASE + GRF_GPIO1A_E);
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/* set the emmc clock(GPIO1B1) drive strength to 23.7ma */
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/* set the emmc cmd(GPIO1B2) drive strength to 14.2ma */
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writel(0x00060002, GRF_BASE + GRF_GPIO1B_DS2);
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writel(0x003C0038, GRF_BASE + GRF_GPIO1B_E);
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}
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#endif
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/* Enable PD_VO (default disable at reset) */
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rk_clrreg(PMU_PWRDN_CON, 1 << 13);
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#ifdef CONFIG_SPL_BUILD
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/* Set cpu qos priority */
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writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY);
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#if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \
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(CONFIG_DEBUG_UART_BASE != 0xff160000) || \
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(CONFIG_DEBUG_UART_CHANNEL != 0)
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static struct px30_grf * const grf = (void *)GRF_BASE;
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/* fix sdmmc pinmux if not using uart2-channel0 as debug uart */
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rk_clrsetreg(&grf->gpio1dl_iomux,
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GPIO1D3_MASK | GPIO1D2_MASK,
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GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT |
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GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT);
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rk_clrsetreg(&grf->gpio1dh_iomux,
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GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK,
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GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT |
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GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT |
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GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT |
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GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
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#endif
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#endif
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/* Enable PD_VO (default disable at reset) */
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rk_clrreg(PMU_PWRDN_CON, 1 << 13);
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/* Disable video phy bandgap by default */
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writel(0x82, VIDEO_PHY_BASE + 0x0000);
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writel(0x05, VIDEO_PHY_BASE + 0x03ac);
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/* Clear the force_jtag */
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rk_clrreg(GRF_CPU_CON1, 1 << 7);
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grf_vccio6_vsel_init();
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if (soc_is_px30s()) {
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/* set usb2phy parameter */
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writel(0x04, USBPHY_GRF_BASE + 0x8000);
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writel(0x46, USBPHY_GRF_BASE + 0x8004);
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writel(0xdb, USBPHY_GRF_BASE + 0x8008);
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writel(0x04, USBPHY_GRF_BASE + 0x8400);
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writel(0x46, USBPHY_GRF_BASE + 0x8404);
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writel(0xdb, USBPHY_GRF_BASE + 0x8408);
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}
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return 0;
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}
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#define GRF_BASE 0xff140000
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#define UART2_BASE 0xff160000
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#define CRU_BASE 0xff2b0000
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void board_debug_uart_init(void)
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{
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static struct px30_grf * const grf = (void *)GRF_BASE;
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static struct px30_cru * const cru = (void *)CRU_BASE;
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000)
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/* uart_sel_clk default select 24MHz */
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rk_clrsetreg(&cru->clksel_con[34],
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UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK,
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UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0);
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rk_clrsetreg(&cru->clksel_con[35],
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UART1_CLK_SEL_MASK,
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UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio1cl_iomux,
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GPIO1C1_MASK | GPIO1C0_MASK,
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GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
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GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
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/* uart_sel_clk default select 24MHz */
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rk_clrsetreg(&cru->clksel_con[46],
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UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK,
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UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0);
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rk_clrsetreg(&cru->clksel_con[47],
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UART5_CLK_SEL_MASK,
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UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio3al_iomux,
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GPIO3A2_MASK | GPIO3A1_MASK,
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GPIO3A2_UART5_TX << GPIO3A2_SHIFT |
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GPIO3A1_UART5_RX << GPIO3A1_SHIFT);
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#else
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/* GRF_IOFUNC_CON0 */
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enum {
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CON_IOMUX_UART2SEL_SHIFT = 10,
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CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT,
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CON_IOMUX_UART2SEL_M0 = 0,
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CON_IOMUX_UART2SEL_M1,
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CON_IOMUX_UART2SEL_USBPHY,
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};
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/* uart_sel_clk default select 24MHz */
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rk_clrsetreg(&cru->clksel_con[37],
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UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK,
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UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0);
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rk_clrsetreg(&cru->clksel_con[38],
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UART2_CLK_SEL_MASK,
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UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT);
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#if (CONFIG_DEBUG_UART2_CHANNEL == 1)
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/* Enable early UART2 */
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rk_clrsetreg(&grf->iofunc_con0,
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CON_IOMUX_UART2SEL_MASK,
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CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT);
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/*
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* Set iomux to UART2_M0 and UART2_M1.
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* Because uart2_rxm0 and uart2_txm0 are default reset value,
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* so only need set uart2_rxm1 and uart2_txm1 here.
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*/
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rk_clrsetreg(&grf->gpio2bh_iomux,
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GPIO2B6_MASK | GPIO2B4_MASK,
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GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT |
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GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT);
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#else
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rk_clrsetreg(&grf->iofunc_con0,
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CON_IOMUX_UART2SEL_MASK,
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CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT);
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rk_clrsetreg(&grf->gpio1dl_iomux,
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GPIO1D3_MASK | GPIO1D2_MASK,
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GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT |
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GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT);
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#endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */
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#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
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}
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int set_armclk_rate(void)
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{
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struct px30_clk_priv *priv;
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struct clk clk;
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int ret;
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ret = rockchip_get_clk(&clk.dev);
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if (ret) {
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printf("Failed to get clk dev\n");
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return ret;
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}
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clk.id = ARMCLK;
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priv = dev_get_priv(clk.dev);
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ret = clk_set_rate(&clk, priv->armclk_hz);
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if (ret < 0) {
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printf("Failed to set armclk %lu\n", priv->armclk_hz);
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return ret;
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}
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priv->set_armclk_rate = true;
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return 0;
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}
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static int fdt_fixup_cpu_opp_table(const void *blob)
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{
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int opp_node, cpu_node, sub_node;
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int len;
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u32 phandle;
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u32 *pp;
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/* Replace opp table */
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opp_node = fdt_path_offset(blob, "/px30s-cpu0-opp-table");
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if (opp_node < 0) {
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printf("Failed to get px30s-cpu0-opp-table node\n");
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return -EINVAL;
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}
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phandle = fdt_get_phandle(blob, opp_node);
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if (!phandle) {
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printf("Failed to get cpu opp table phandle\n");
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return -EINVAL;
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}
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cpu_node = fdt_path_offset(blob, "/cpus");
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if (cpu_node < 0) {
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printf("Failed to get cpus node\n");
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return -EINVAL;
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}
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fdt_for_each_subnode(sub_node, blob, cpu_node) {
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pp = (u32 *)fdt_getprop(blob, sub_node, "operating-points-v2",
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&len);
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if (!pp)
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continue;
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pp[0] = cpu_to_fdt32(phandle);
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}
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return 0;
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}
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static int fdt_fixup_dmc_opp_table(const void *blob)
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{
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int opp_node, dmc_node;
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int len;
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u32 phandle;
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u32 *pp;
|
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opp_node = fdt_path_offset(blob, "/px30s-dmc-opp-table");
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if (opp_node < 0) {
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printf("Failed to get px30s-dmc-opp-table node\n");
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return -EINVAL;
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}
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phandle = fdt_get_phandle(blob, opp_node);
|
if (!phandle) {
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printf("Failed to get dmc opp table phandle\n");
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return -EINVAL;
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}
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dmc_node = fdt_path_offset(blob, "/dmc");
|
if (dmc_node < 0) {
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printf("Failed to get dmc node\n");
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return -EINVAL;
|
}
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pp = (u32 *)fdt_getprop(blob, dmc_node, "operating-points-v2", &len);
|
if (!pp)
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return 0;
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pp[0] = cpu_to_fdt32(phandle);
|
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return 0;
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}
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|
static int fdt_fixup_gpu_opp_table(const void *blob)
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{
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int opp_node, gpu_node;
|
int len;
|
u32 phandle;
|
u32 *pp;
|
|
opp_node = fdt_path_offset(blob, "/px30s-gpu-opp-table");
|
if (opp_node < 0) {
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printf("Failed to get px30s-gpu-opp-table node\n");
|
return -EINVAL;
|
}
|
|
phandle = fdt_get_phandle(blob, opp_node);
|
if (!phandle) {
|
printf("Failed to get gpu opp table phandle\n");
|
return -EINVAL;
|
}
|
|
gpu_node = fdt_path_offset(blob, "/gpu@ff400000");
|
if (gpu_node < 0) {
|
printf("Failed to get gpu node\n");
|
return -EINVAL;
|
}
|
|
pp = (u32 *)fdt_getprop(blob, gpu_node, "operating-points-v2", &len);
|
if (!pp)
|
return 0;
|
pp[0] = cpu_to_fdt32(phandle);
|
|
return 0;
|
}
|
|
static void fixup_pcfg_drive_strength(const void *blob, int noffset)
|
{
|
u32 *ds, *dss;
|
u32 val;
|
|
dss = (u32 *)fdt_getprop(blob, noffset, "drive-strength-s", NULL);
|
if (!dss)
|
return;
|
|
val = dss[0];
|
ds = (u32 *)fdt_getprop(blob, noffset, "drive-strength", NULL);
|
if (ds) {
|
ds[0] = val;
|
} else {
|
if (fdt_setprop((void *)blob, noffset,
|
"drive-strength", &val, 4) < 0)
|
printf("Failed to add drive-strength prop\n");
|
}
|
}
|
|
static int fdt_fixup_pcfg(const void *blob)
|
{
|
int depth1_node;
|
int depth2_node;
|
int root_node;
|
|
root_node = fdt_path_offset(blob, "/");
|
if (root_node < 0)
|
return root_node;
|
|
fdt_for_each_subnode(depth1_node, blob, root_node) {
|
debug("depth1: %s\n", fdt_get_name(blob, depth1_node, NULL));
|
fixup_pcfg_drive_strength(blob, depth1_node);
|
fdt_for_each_subnode(depth2_node, blob, depth1_node) {
|
debug(" depth2: %s\n",
|
fdt_get_name(blob, depth2_node, NULL));
|
fixup_pcfg_drive_strength(blob, depth2_node);
|
}
|
}
|
|
return 0;
|
}
|
|
static int fdt_fixup_bus_apll(const void *blob)
|
{
|
char path[] = "/bus-apll";
|
|
do_fixup_by_path((void *)blob, path, "status", "disabled", sizeof("disabled"), 0);
|
|
return 0;
|
}
|
|
static int fdt_fixup_cpu_gpu_clk(const void *blob)
|
{
|
int cpu_node, gpu_node, scmi_clk_node;
|
int len;
|
u32 phandle;
|
u32 *pp;
|
|
scmi_clk_node = fdt_path_offset(blob, "/firmware/scmi/protocol@14");
|
if (scmi_clk_node < 0) {
|
printf("Failed to get px30s scmi clk node\n");
|
return -EINVAL;
|
}
|
|
phandle = fdt_get_phandle(blob, scmi_clk_node);
|
if (!phandle)
|
return 0;
|
|
cpu_node = fdt_path_offset(blob, "/cpus/cpu@0");
|
if (cpu_node < 0) {
|
printf("Failed to get px30s cpu node\n");
|
return -EINVAL;
|
}
|
/*
|
* before fixed:
|
* clocks = <&cru ARMCLK>;
|
* after fixed:
|
* clocks = <&scmi_clk 0>;
|
*/
|
pp = (u32 *)fdt_getprop(blob, cpu_node,
|
"clocks",
|
&len);
|
if (!pp)
|
return 0;
|
if ((len / 8) >= 1) {
|
pp[0] = cpu_to_fdt32(phandle);
|
pp[1] = cpu_to_fdt32(0);
|
}
|
|
gpu_node = fdt_path_offset(blob, "/gpu@ff400000");
|
if (gpu_node < 0) {
|
printf("Failed to get px30s gpu node\n");
|
return -EINVAL;
|
}
|
/*
|
* before fixed:
|
* clocks = <&cru SCLK_GPU>;
|
* after fixed:
|
* clocks = <&scmi_clk 1>;
|
*/
|
pp = (u32 *)fdt_getprop(blob, gpu_node,
|
"clocks",
|
&len);
|
if (!pp)
|
return 0;
|
if ((len / 8) >= 1) {
|
pp[0] = cpu_to_fdt32(phandle);
|
pp[1] = cpu_to_fdt32(1);
|
}
|
return 0;
|
}
|
|
static int fdt_fixup_i2s_soft_reset(const void *blob)
|
{
|
int node;
|
int len;
|
u32 *pp;
|
|
node = fdt_path_offset(blob, "/i2s@ff060000");
|
if (node < 0) {
|
printf("Failed to get px30s i2s node\n");
|
return -EINVAL;
|
}
|
|
/*
|
* before fixed:
|
* resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
|
* after fixed:
|
* resets = <&cru SRST_I2S0_TX>, <&cru 128>;
|
*/
|
pp = (u32 *)fdt_getprop(blob, node,
|
"resets",
|
&len);
|
if (!pp)
|
return 0;
|
if ((len / 8) >= 2)
|
pp[3] = cpu_to_fdt32(128);
|
|
return 0;
|
}
|
|
#define RKPM_SLP_ARMPD BIT(0)
|
#define RKPM_SLP_ARMOFF BIT(1)
|
#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
|
#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
|
|
static int fdt_fixup_rockchip_suspend(const void *blob)
|
{
|
int suspend_node;
|
u32 *data, mode;
|
|
/* Replace opp table */
|
suspend_node = fdt_path_offset(blob, "/rockchip-suspend");
|
if (suspend_node < 0) {
|
printf("Failed to get rockchip-suspend node\n");
|
return -EINVAL;
|
}
|
|
data = (u32 *)fdt_getprop(blob, suspend_node,
|
"rockchip,sleep-mode-config", NULL);
|
if (!data)
|
return 0;
|
|
mode = fdt32_to_cpu(*data);
|
mode &= ~RKPM_SLP_ARMOFF_LOGOFF;
|
mode |= RKPM_SLP_ARMOFF;
|
*data = cpu_to_fdt32(mode);
|
|
if (fdt_setprop((void *)blob, suspend_node,
|
"rockchip,sleep-mode-config", data, sizeof(*data)))
|
printf("Failed to set rockchip,sleep-mode-config = 0x%x\n", mode);
|
else
|
debug("set rockchip,sleep-mode-config = 0x%x\n", mode);
|
|
return 0;
|
}
|
|
static void fixup_regulators_px30s(const void *blob, int reg_node)
|
{
|
const char *name;
|
int mem_node;
|
int suspend;
|
u32 *min, *max;
|
|
min = (u32 *)fdt_getprop(blob, reg_node,
|
"regulator-min-microvolt", NULL);
|
max = (u32 *)fdt_getprop(blob, reg_node,
|
"regulator-max-microvolt", NULL);
|
if (!min || !max)
|
return;
|
|
name = fdt_getprop(blob, reg_node, "regulator-name", NULL);
|
|
debug("%s: name: %s, min %duV, max %duV\n",
|
name, fdt_get_name(blob, reg_node, NULL),
|
fdt32_to_cpu(min[0]), fdt32_to_cpu(max[0]));
|
|
/* 1. fixed volt: 1.0v => 0.9v */
|
if (*min == *max && fdt32_to_cpu(min[0]) == 1000000) {
|
mem_node = fdt_subnode_offset(blob, reg_node,
|
"regulator-state-mem");
|
if (mem_node < 0)
|
return;
|
|
suspend = cpu_to_fdt32(900000);
|
if (fdt_setprop((void *)blob, mem_node,
|
"regulator-suspend-microvolt",
|
&suspend, sizeof(suspend)))
|
printf("Failed to set %s suspend 0.9V\n", name);
|
else
|
debug("%s: set suspend volt 0.9V\n", name);
|
|
min[0] = cpu_to_fdt32(900000);
|
max[0] = cpu_to_fdt32(900000);
|
debug("%s: min/max 1.0v => 0.9v\n",
|
fdt_get_name(blob, reg_node, NULL));
|
}
|
|
/* 2. vdd_logic suspend: any => 0.85v */
|
if (!strcmp(name, "vdd_logic")) {
|
mem_node = fdt_subnode_offset(blob, reg_node,
|
"regulator-state-mem");
|
if (mem_node < 0)
|
return;
|
|
suspend = cpu_to_fdt32(850000);
|
if (fdt_setprop((void *)blob, mem_node,
|
"regulator-suspend-microvolt",
|
&suspend, sizeof(suspend)))
|
printf("Failed to set vdd_logic suspend 0.85V\n");
|
else
|
debug("vdd_logic: set suspend volt 0.85V\n");
|
}
|
}
|
|
static void fixup_regulators_px30(const void *blob, int reg_node)
|
{
|
const char *name;
|
int mem_node;
|
|
name = fdt_getprop(blob, reg_node, "regulator-name", NULL);
|
if (!name)
|
return;
|
|
/* regulator-off-in-suspend => regulator-on-in-suspend */
|
if (!strcmp(name, "vdd_logic") ||
|
!strcmp(name, "vcc_3v0") ||
|
!strcmp(name, "vcc_1v0") ||
|
!strcmp(name, "vccio_sd") ||
|
!strcmp(name, "vcc_sd")) {
|
mem_node = fdt_subnode_offset(blob, reg_node,
|
"regulator-state-mem");
|
if (mem_node < 0)
|
return;
|
|
fdt_delprop((void *)blob, mem_node, "regulator-off-in-suspend");
|
if (fdt_setprop((void *)blob, mem_node,
|
"regulator-on-in-suspend", NULL, 0))
|
printf("Failed to set regulator(%s) on in suspend\n", name);
|
else
|
debug("set regulator(%s) on in suspend\n", name);
|
}
|
}
|
|
static void fixup_regulators(const void *blob, int pmic_node)
|
{
|
int parent_node;
|
int reg_node;
|
|
parent_node = fdt_subnode_offset(blob, pmic_node, "regulators");
|
if (parent_node < 0)
|
return;
|
|
fdt_for_each_subnode(reg_node, blob, parent_node) {
|
if (soc_is_px30s())
|
fixup_regulators_px30s(blob, reg_node);
|
else if (soc_is_px30())
|
fixup_regulators_px30(blob, reg_node);
|
}
|
}
|
|
/* Assume that: all regulators are from rk809/817 */
|
static int fdt_fixup_regulator(const void *blob)
|
{
|
const char *name;
|
int i2c_node;
|
int pmic_node;
|
int root_node;
|
|
root_node = fdt_path_offset(blob, "/");
|
if (root_node < 0)
|
return root_node;
|
|
fdt_for_each_subnode(i2c_node, blob, root_node) {
|
name = fdt_get_name(blob, i2c_node, NULL);
|
debug("depth1: %s\n", name);
|
if (!strncmp(name, "i2c@", 4)) {
|
fdt_for_each_subnode(pmic_node, blob, i2c_node) {
|
name = fdt_get_name(blob, pmic_node, NULL);
|
debug("depth2: %s\n", name);
|
if (!strncmp(name, "pmic@20", 7)) {
|
fixup_regulators(blob, pmic_node);
|
return 0;
|
}
|
}
|
}
|
}
|
|
return 0;
|
}
|
|
int rk_board_fdt_fixup(const void *blob)
|
{
|
if (soc_is_px30s()) {
|
fdt_increase_size((void *)blob, SZ_8K);
|
fdt_fixup_cpu_opp_table(blob);
|
fdt_fixup_dmc_opp_table(blob);
|
fdt_fixup_gpu_opp_table(blob);
|
fdt_fixup_pcfg(blob);
|
fdt_fixup_bus_apll(blob);
|
fdt_fixup_cpu_gpu_clk(blob);
|
fdt_fixup_i2s_soft_reset(blob);
|
} else if (soc_is_px30()) {
|
fdt_fixup_rockchip_suspend(blob);
|
}
|
|
fdt_fixup_regulator(blob);
|
|
return 0;
|
}
|
|
int rk_board_early_fdt_fixup(const void *blob)
|
{
|
rk_board_fdt_fixup(blob);
|
|
return 0;
|
}
|
|
void do_board_download(void)
|
{
|
/*
|
* Maskrom download can prevent to flash px30s board with px30
|
* update.img, because px30 ddr.bin can't work on px30s which is
|
* early than download action.
|
*
|
* Let's handle that early than outside generic download.
|
*/
|
if (soc_is_px30s()) {
|
printf("Rockusb is disabled, entering bootrom...\n");
|
flushc();
|
run_command("rbrom", 0);
|
}
|
}
|
|
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC_FSP)
|
int rk_board_init(void)
|
{
|
struct udevice *dev;
|
u32 ret = 0;
|
|
ret = uclass_get_device_by_driver(UCLASS_DMC, DM_GET_DRIVER(dmc_fsp), &dev);
|
if (ret) {
|
printf("dmc_fsp failed, ret=%d\n", ret);
|
return 0;
|
}
|
|
return 0;
|
}
|
#endif
|
