Device Tree Clock bindings for arch-vt8500
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
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"wm,wm8650-pll-clock" - for a WM8650 PLL clock
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"wm,wm8750-pll-clock" - for a WM8750 PLL clock
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"wm,wm8850-pll-clock" - for a WM8850 PLL clock
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"via,vt8500-device-clock" - for a VT/WM device clock
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Required properties for PLL clocks:
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- reg : shall be the control register offset from PMC base for the pll clock.
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- clocks : shall be the input parent clock phandle for the clock. This should
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be the reference clock.
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- #clock-cells : from common clock binding; shall be set to 0.
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Required properties for device clocks:
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- clocks : shall be the input parent clock phandle for the clock. This should
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be a pll output.
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- #clock-cells : from common clock binding; shall be set to 0.
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Device Clocks
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Device clocks are required to have one or both of the following sets of
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properties:
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Gated device clocks:
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Required properties:
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- enable-reg : shall be the register offset from PMC base for the enable
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register.
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- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
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Divisor device clocks:
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Required property:
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- divisor-reg : shall be the register offset from PMC base for the divisor
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register.
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Optional property:
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- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
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if not specified.
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For example:
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ref25: ref25M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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plla: plla {
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#clock-cells = <0>;
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compatible = "wm,wm8650-pll-clock";
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clocks = <&ref25>;
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reg = <0x200>;
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};
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sdhc: sdhc {
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#clock-cells = <0>;
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compatible = "via,vt8500-device-clock";
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clocks = <&pllb>;
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divisor-reg = <0x328>;
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divisor-mask = <0x3f>;
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enable-reg = <0x254>;
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enable-bit = <18>;
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};
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