/*
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* Rockchip resume header (API from kernel to embedded code)
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*
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* Copyright (c) 2014 Google, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MACH_ROCKCHIP_RK3288_RESUME_H
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#define __MACH_ROCKCHIP_RK3288_RESUME_H
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#define RK3288_NUM_DDR_PORTS 2
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#define RK3288_MAX_PWM_REGS 3
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#define RK3288_MAX_DDR_PHY_DLL_REGS 7
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#define RK3288_MAX_DDR_CTRL_REGS 64
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#define RK3288_MAX_DDR_PHY_REGS 29
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#define RK3288_MAX_DDR_MSCH_REGS 6
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#define RK3288_MAX_DDR_PHY_ZQCR_REGS 2
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#define RK3288_BOGUS_OFFSET 0xffffffff
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/**
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* rk3288_ddr_save - Parameters needed to reinit SDRAM after suspend
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*
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* This structure contains data needed to restore SDRAM after suspend.
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* Generally:
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* - There are two controllers and we need to save data for both. We save
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* the same registers for both, so you see two sets of values and one sets
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* of offsets (the register offset from the base of the controller).
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* There are a few registers that are always the same for both controllers
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* so we only save one set of values.
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*
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* Offsets are saved at init time and vals are saved on each suspend.
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*
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* NOTE: offsets are u32 values right now to keep everything 32-bit and avoid
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* 8-bit and 16-bit access problems in PMU SRAM (see WARNING below).
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* Technically, though, 8-bit and 16-bit _reads_ seem to work, so as long as
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* we were careful in setting things up we could possibly save some memory by
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* storing 16-bit offsets. We can investigate if we ever get that tight on
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* space.
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*/
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struct rk3288_ddr_save_data {
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u32 pwm_addrs[RK3288_MAX_PWM_REGS];
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u32 pwm_vals[RK3288_MAX_PWM_REGS];
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u32 phy_dll_offsets[RK3288_MAX_DDR_PHY_DLL_REGS];
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u32 phy_dll_vals[RK3288_NUM_DDR_PORTS][RK3288_MAX_DDR_PHY_DLL_REGS];
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u32 ctrl_offsets[RK3288_MAX_DDR_CTRL_REGS];
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u32 ctrl_vals[RK3288_MAX_DDR_CTRL_REGS]; /* Both same */
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u32 phy_offsets[RK3288_MAX_DDR_PHY_REGS];
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u32 phy_vals[RK3288_NUM_DDR_PORTS][RK3288_MAX_DDR_PHY_REGS];
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u32 msch_offsets[RK3288_MAX_DDR_MSCH_REGS];
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u32 msch_vals[RK3288_NUM_DDR_PORTS][RK3288_MAX_DDR_MSCH_REGS];
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u32 phy_zqcr_offsets[RK3288_MAX_DDR_PHY_ZQCR_REGS];
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u32 phy_zqcr_vals[RK3288_MAX_DDR_PHY_ZQCR_REGS]; /* Both same */
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};
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/**
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* rk3288_resume_params - Parameter space for the resume code
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*
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* This structure is at the start of the resume blob and is used to communicate
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* between the resume blob and the callers.
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*
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* WARNING: This structure is sitting in PMU SRAM. If you try to write to that
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* memory using an 8-bit access (or even 16-bit) you'll get an imprecise data
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* abort and it will be very hard to debug. Keep everything in here as 32-bit
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* wide and aligned. YOU'VE BEEN WARNED.
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*
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* @resume_loc: The value here should be the resume address that the CPU
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* is programmed to go to at resume time.
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*
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* @l2ctlr_f: If non-zero we'll set l2ctlr at resume time.
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* @l2ctlr: The value to set l2ctlr to at resume time.
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*
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* @ddr_resume_f True if we should resume DDR.
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* @ddr_save_data: Data for save / restore of DDR.
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*
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* @cpu_resume: The function to jump to when we're all done.
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*/
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struct rk3288_resume_params {
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/* This is compiled in and can be read to find the resume location */
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__noreturn void (*resume_loc)(void);
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/* Filled in by the client of the resume code */
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u32 l2ctlr_f; /* u32 not bool to avoid 8-bit SRAM access */
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u32 l2ctlr;
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u32 ddr_resume_f; /* u32 not bool to avoid 8-bit SRAM access */
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struct rk3288_ddr_save_data ddr_save_data;
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__noreturn void (*cpu_resume)(void);
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};
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#endif /* __MACH_ROCKCHIP_RK3288_RESUME_H */
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