/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Chris Zhong <zyw@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __MACH_ROCKCHIP_RK3288_DDR_H
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#define __MACH_ROCKCHIP_RK3288_DDR_H
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/* DDR pctl register */
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#define DDR_PCTL_SCFG 0x0000
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#define DDR_PCTL_SCTL 0x0004
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#define DDR_PCTL_STAT 0x0008
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#define DDR_PCTL_MCMD 0x0040
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#define DDR_PCTL_POWCTL 0x0044
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#define DDR_PCTL_POWSTAT 0x0048
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#define DDR_PCTL_CMDTSTATEN 0x0050
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#define DDR_PCTL_MRRCFG0 0x0060
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#define DDR_PCTL_MRRSTAT0 0x0064
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#define DDR_PCTL_MRRSTAT1 0x0068
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#define DDR_PCTL_MCFG1 0x007c
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#define DDR_PCTL_MCFG 0x0080
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#define DDR_PCTL_PPCFG 0x0084
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#define DDR_PCTL_TOGCNT1U 0x00c0
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#define DDR_PCTL_TINIT 0x00c4
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#define DDR_PCTL_TRSTH 0x00c8
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#define DDR_PCTL_TOGCNT100N 0x00cc
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#define DDR_PCTL_TREFI 0x00d0
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#define DDR_PCTL_TMRD 0x00d4
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#define DDR_PCTL_TRFC 0x00d8
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#define DDR_PCTL_TRP 0x00dc
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#define DDR_PCTL_TRTW 0x00e0
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#define DDR_PCTL_TAL 0x00e4
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#define DDR_PCTL_TCL 0x00e8
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#define DDR_PCTL_TCWL 0x00ec
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#define DDR_PCTL_TRAS 0x00f0
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#define DDR_PCTL_TRC 0x00f4
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#define DDR_PCTL_TRCD 0x00f8
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#define DDR_PCTL_TRRD 0x00fc
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#define DDR_PCTL_TRTP 0x0100
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#define DDR_PCTL_TWR 0x0104
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#define DDR_PCTL_TWTR 0x0108
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#define DDR_PCTL_TEXSR 0x010c
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#define DDR_PCTL_TXP 0x0110
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#define DDR_PCTL_TXPDLL 0x0114
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#define DDR_PCTL_TZQCS 0x0118
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#define DDR_PCTL_TZQCSI 0x011c
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#define DDR_PCTL_TDQS 0x0120
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#define DDR_PCTL_TCKSRE 0x0124
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#define DDR_PCTL_TCKSRX 0x0128
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#define DDR_PCTL_TCKE 0x012c
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#define DDR_PCTL_TMOD 0x0130
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#define DDR_PCTL_TRSTL 0x0134
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#define DDR_PCTL_TZQCL 0x0138
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#define DDR_PCTL_TMRR 0x013c
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#define DDR_PCTL_TCKESR 0x0140
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#define DDR_PCTL_TDPD 0x0144
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#define DDR_PCTL_DFITCTRLDELAY 0x0240
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#define DDR_PCTL_DFIODTCFG 0x0244
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#define DDR_PCTL_DFIODTCFG1 0x0248
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#define DDR_PCTL_DFIODTRANKMAP 0x024c
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#define DDR_PCTL_DFITPHYWRDATA 0x0250
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#define DDR_PCTL_DFITPHYWRLAT 0x0254
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#define DDR_PCTL_DFITRDDATAEN 0x0260
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#define DDR_PCTL_DFITPHYRDLAT 0x0264
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#define DDR_PCTL_DFITPHYUPDTYPE0 0x0270
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#define DDR_PCTL_DFITPHYUPDTYPE1 0x0274
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#define DDR_PCTL_DFITPHYUPDTYPE2 0x0278
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#define DDR_PCTL_DFITPHYUPDTYPE3 0x027c
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#define DDR_PCTL_DFITCTRLUPDMIN 0x0280
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#define DDR_PCTL_DFITCTRLUPDMAX 0x0284
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#define DDR_PCTL_DFITCTRLUPDDLY 0x0288
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#define DDR_PCTL_DFIUPDCFG 0x0290
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#define DDR_PCTL_DFITREFMSKI 0x0294
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#define DDR_PCTL_DFITCTRLUPDI 0x0298
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#define DDR_PCTL_DFISTCFG0 0x02c4
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#define DDR_PCTL_DFISTCFG1 0x02c8
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#define DDR_PCTL_DFITDRAMCLKEN 0x02d0
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#define DDR_PCTL_DFITDRAMCLKDIS 0x02d4
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#define DDR_PCTL_DFISTCFG2 0x02d8
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#define DDR_PCTL_DFILPCFG0 0x02f0
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/* DDR phy register */
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#define DDR_PUBL_RIDR 0x0000
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#define DDR_PUBL_PIR 0x0004
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#define DDR_PUBL_PGCR 0x0008
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#define DDR_PUBL_PGSR 0x000c
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#define DDR_PUBL_DLLGCR 0x0010
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#define DDR_PUBL_ACDLLCR 0x0014
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#define DDR_PUBL_PTR0 0x0018
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#define DDR_PUBL_PTR1 0x001c
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#define DDR_PUBL_PTR2 0x0020
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#define DDR_PUBL_ACIOCR 0x0024
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#define DDR_PUBL_DXCCR 0x0028
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#define DDR_PUBL_DSGCR 0x002c
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#define DDR_PUBL_DCR 0x0030
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#define DDR_PUBL_DTPR0 0x0034
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#define DDR_PUBL_DTPR1 0x0038
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#define DDR_PUBL_DTPR2 0x003c
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#define DDR_PUBL_MR0 0x0040
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#define DDR_PUBL_MR1 0x0044
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#define DDR_PUBL_MR2 0x0048
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#define DDR_PUBL_MR3 0x004c
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#define DDR_PUBL_ODTCR 0x0050
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#define DDR_PUBL_DTAR 0x0054
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#define DDR_PUBL_ZQ0CR0 0x0180
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#define DDR_PUBL_ZQ0CR1 0x0184
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#define DDR_PUBL_ZQ1CR0 0x0190
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#define DDR_PUBL_DX0GCR 0x01c0
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#define DDR_PUBL_DX0GSR0 0x01c4
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#define DDR_PUBL_DX0GSR1 0x01c8
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#define DDR_PUBL_DX0DLLCR 0x01cc
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#define DDR_PUBL_DX0DQTR 0x01d0
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#define DDR_PUBL_DX0DQSTR 0x01d4
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#define DDR_PUBL_DX1GCR 0x0200
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#define DDR_PUBL_DX1GSR0 0x0204
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#define DDR_PUBL_DX1GSR1 0x0208
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#define DDR_PUBL_DX1DLLCR 0x020c
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#define DDR_PUBL_DX1DQTR 0x0210
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#define DDR_PUBL_DX1DQSTR 0x0214
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#define DDR_PUBL_DX2GCR 0x0240
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#define DDR_PUBL_DX2GSR0 0x0244
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#define DDR_PUBL_DX2GSR1 0x0248
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#define DDR_PUBL_DX2DLLCR 0x024c
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#define DDR_PUBL_DX2DQTR 0x0250
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#define DDR_PUBL_DX2DQSTR 0x0254
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#define DDR_PUBL_DX3GCR 0x0280
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#define DDR_PUBL_DX3GSR0 0x0284
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#define DDR_PUBL_DX3GSR1 0x0288
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#define DDR_PUBL_DX3DLLCR 0x028c
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#define DDR_PUBL_DX3DQTR 0x0290
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#define DDR_PUBL_DX3DQSTR 0x0294
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/* DDR msch register */
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#define DDR_MSCH_DDRCONF 0x0008
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#define DDR_MSCH_DDRTIMING 0x000c
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#define DDR_MSCH_DDRMODE 0x0010
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#define DDR_MSCH_READLATENCY 0x0014
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#define DDR_MSCH_ACTIVATE 0x0038
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#define DDR_MSCH_DEVTODEV 0x003c
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#define DLLSRST BIT(30)
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#define POWER_UP_START BIT(0)
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#define POWER_UP_DONE BIT(0)
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#define DDR0IO_RET_DE_REQ BIT(21)
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#define DDR0I1_RET_DE_REQ BIT(22)
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#define PCTL_STAT_MSK (7)
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#define LP_TRIG_VAL(n) (((n) >> 4) & 7)
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/* SCTL */
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#define INIT_STATE (0)
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#define CFG_STATE (1)
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#define GO_STATE (2)
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#define SLEEP_STATE (3)
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#define WAKEUP_STATE (4)
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/* STAT */
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#define LP_TRIG_VAL(n) (((n) >> 4) & 7)
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#define PCTL_STAT_MSK (7)
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#define INIT_MEM (0)
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#define CONFIG (1)
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#define CONFIG_REQ (2)
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#define ACCESS (3)
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#define ACCESS_REQ (4)
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#define LOW_POWER (5)
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#define LOW_POWER_ENTRY_REQ (6)
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#define LOW_POWER_EXIT_REQ (7)
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/* PGSR */
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#define PGSR_IDONE (1 << 0)
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#define PGSR_DLDONE (1 << 1)
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#define PGSR_ZCDONE (1 << 2)
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#define PGSR_DIDONE (1 << 3)
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#define PGSR_DTDONE (1 << 4)
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#define PGSR_DTERR (1 << 5)
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#define PGSR_DTIERR (1 << 6)
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#define PGSR_DFTERR (1 << 7)
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#define PGSR_RVERR (1 << 8)
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#define PGSR_RVEIRR (1 << 9)
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/* PIR */
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#define PIR_INIT (1 << 0)
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#define PIR_DLLSRST (1 << 1)
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#define PIR_DLLLOCK (1 << 2)
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#define PIR_ZCAL (1 << 3)
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#define PIR_ITMSRST (1 << 4)
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#define PIR_DRAMRST (1 << 5)
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#define PIR_DRAMINIT (1 << 6)
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#define PIR_QSTRN (1 << 7)
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#define PIR_RVTRN (1 << 8)
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#define PIR_ICPC (1 << 16)
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#define PIR_DLLBYP (1 << 17)
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#define PIR_CTLDINIT (1 << 18)
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#define PIR_CLRSR (1 << 28)
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#define PIR_LOCKBYP (1 << 29)
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#define PIR_ZCALBYP (1 << 30)
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#define PIR_INITBYP (1u << 31)
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#endif /* __MACH_ROCKCHIP_RK3288_DDR_H */
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