/*
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* (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ROCKCHIP_VOP_H_
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#define _ROCKCHIP_VOP_H_
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#include "rockchip_display.h"
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#include <asm/gpio.h>
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#define VOP_REG_SUPPORT(vop, reg) \
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(reg.mask && \
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(!reg.major || \
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(reg.major == VOP_MAJOR(vop->version) && \
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reg.begin_minor <= VOP_MINOR(vop->version) && \
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reg.end_minor >= VOP_MINOR(vop->version))))
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#define VOP_WIN_SUPPORT(vop, win, name) \
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VOP_REG_SUPPORT(vop, win->name)
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#define VOP_CTRL_SUPPORT(vop, name) \
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VOP_REG_SUPPORT(vop, vop->ctrl->name)
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#define __REG_SET(x, off, mask, shift, v, write_mask) \
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vop_mask_write(x, off, mask, shift, v, write_mask)
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#define _REG_SET(vop, name, off, reg, mask, v) \
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do { \
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if (VOP_REG_SUPPORT(vop, reg)) \
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__REG_SET(vop, off + reg.offset, mask, reg.shift, \
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v, reg.write_mask); \
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else \
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debug("Warning: not support "#name"\n"); \
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} while(0)
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#define REG_SET(x, name, off, reg, v) \
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_REG_SET(x, name, off, reg, reg.mask, v)
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#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
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_REG_SET(x, name, off, reg, reg.mask & mask, v)
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#define VOP_WIN_SET(x, name, v) \
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REG_SET(x, name, x->win_offset, x->win->name, v)
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#define VOP_WIN_SET_EXT(x, ext, name, v) \
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REG_SET(x, name, x->win_offset, x->win->ext->name, v)
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#define VOP_SCL_SET(x, name, v) \
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REG_SET(x, name, x->win_offset, x->win->scl->name, v)
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#define VOP_SCL_SET_EXT(x, name, v) \
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REG_SET(x, name, x->win_offset, x->win->scl->ext->name, v)
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#define VOP_CTRL_SET(x, name, v) \
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REG_SET(x, name, 0, (x)->ctrl->name, v)
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#define VOP_LINE_FLAG_SET(x, name, v) \
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REG_SET(x, name, 0, (x)->line_flag->name, v)
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#define VOP_WIN_CSC_SET(x, name, v) \
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REG_SET(x, name, 0, (x)->win_csc->name, v)
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#define VOP_CTRL_GET(x, name) \
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vop_read_reg(x, 0, &vop->ctrl->name)
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#define VOP_WIN_GET(x, name) \
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vop_read_reg(x, vop->win->offset, &vop->win->name)
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#define VOP_GRF_SET(vop, name, v) \
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do { \
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if (vop->grf_ctrl) { \
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vop_grf_writel(vop, vop->grf_ctrl->name, v); \
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} \
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} while (0)
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#define CVBS_PAL_VDISPLAY 288
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enum alpha_mode {
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ALPHA_STRAIGHT,
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ALPHA_INVERSE,
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};
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enum global_blend_mode {
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ALPHA_GLOBAL,
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ALPHA_PER_PIX,
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ALPHA_PER_PIX_GLOBAL,
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};
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enum alpha_cal_mode {
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ALPHA_SATURATION,
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ALPHA_NO_SATURATION,
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};
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enum color_mode {
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ALPHA_SRC_PRE_MUL,
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ALPHA_SRC_NO_PRE_MUL,
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};
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enum factor_mode {
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ALPHA_ZERO,
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ALPHA_ONE,
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ALPHA_SRC,
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ALPHA_SRC_INVERSE,
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ALPHA_SRC_GLOBAL,
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};
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enum scale_mode {
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SCALE_NONE = 0x0,
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SCALE_UP = 0x1,
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SCALE_DOWN = 0x2
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};
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enum lb_mode {
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LB_YUV_3840X5 = 0x0,
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LB_YUV_2560X8 = 0x1,
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LB_RGB_3840X2 = 0x2,
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LB_RGB_2560X4 = 0x3,
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LB_RGB_1920X5 = 0x4,
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LB_RGB_1280X8 = 0x5
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};
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enum sacle_up_mode {
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SCALE_UP_BIL = 0x0,
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SCALE_UP_BIC = 0x1
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};
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enum scale_down_mode {
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SCALE_DOWN_BIL = 0x0,
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SCALE_DOWN_AVG = 0x1
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};
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enum dither_down_mode {
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RGB888_TO_RGB565 = 0x0,
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RGB888_TO_RGB666 = 0x1
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};
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enum dither_down_mode_sel {
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DITHER_DOWN_ALLEGRO = 0x0,
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DITHER_DOWN_FRC = 0x1
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};
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enum vop_csc_format {
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CSC_BT601L,
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CSC_BT709L,
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CSC_BT601F,
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CSC_BT2020,
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};
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#define DSP_BG_SWAP 0x1
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#define DSP_RB_SWAP 0x2
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#define DSP_RG_SWAP 0x4
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#define DSP_DELTA_SWAP 0x8
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#define PRE_DITHER_DOWN_EN(x) ((x) << 0)
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#define DITHER_DOWN_EN(x) ((x) << 1)
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#define DITHER_DOWN_MODE(x) ((x) << 2)
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#define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
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#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
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#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
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#define SCL_MAX_VSKIPLINES 4
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#define MIN_SCL_FT_AFTER_VSKIP 1
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#define VOP_PLANE_NO_SCALING BIT(16)
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static inline uint16_t scl_cal_scale(int src, int dst, int shift)
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{
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return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
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}
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static inline uint16_t scl_cal_scale2(int src, int dst)
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{
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return ((src - 1) << 12) / (dst - 1);
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}
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#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
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#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
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#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
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static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
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int vskiplines)
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{
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int act_height;
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act_height = (src_h + vskiplines - 1) / vskiplines;
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return GET_SCL_FT_BILI_DN(act_height, dst_h);
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}
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static inline enum scale_mode scl_get_scl_mode(int src, int dst)
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{
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if (src < dst)
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return SCALE_UP;
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else if (src > dst)
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return SCALE_DOWN;
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return SCALE_NONE;
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}
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static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
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{
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uint32_t vskiplines;
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for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
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if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
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break;
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return vskiplines;
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}
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static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
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{
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int lb_mode;
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if (width > 2560)
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lb_mode = LB_RGB_3840X2;
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else if (width > 1920)
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lb_mode = LB_RGB_2560X4;
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else if (!is_yuv)
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lb_mode = LB_RGB_1920X5;
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else if (width > 1280)
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lb_mode = LB_YUV_3840X5;
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else
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lb_mode = LB_YUV_2560X8;
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return lb_mode;
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}
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struct vop_reg_data {
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uint32_t offset;
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uint32_t value;
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};
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struct vop_reg {
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uint32_t mask;
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uint32_t offset:17;
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uint32_t shift:5;
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uint32_t begin_minor:4;
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uint32_t end_minor:4;
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uint32_t reserved:2;
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uint32_t major:3;
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uint32_t write_mask:1;
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};
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struct vop_ctrl {
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struct vop_reg standby;
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struct vop_reg axi_outstanding_max_num;
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struct vop_reg axi_max_outstanding_en;
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struct vop_reg htotal_pw;
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struct vop_reg hact_st_end;
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struct vop_reg vtotal_pw;
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struct vop_reg vact_st_end;
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struct vop_reg vact_st_end_f1;
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struct vop_reg vs_st_end_f1;
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struct vop_reg hpost_st_end;
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struct vop_reg vpost_st_end;
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struct vop_reg vpost_st_end_f1;
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struct vop_reg post_scl_factor;
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struct vop_reg post_scl_ctrl;
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struct vop_reg dsp_interlace;
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struct vop_reg global_regdone_en;
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struct vop_reg auto_gate_en;
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struct vop_reg post_lb_mode;
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struct vop_reg dsp_layer_sel;
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struct vop_reg overlay_mode;
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struct vop_reg core_dclk_div;
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struct vop_reg dclk_ddr;
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struct vop_reg p2i_en;
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struct vop_reg hdmi_dclk_out_en;
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struct vop_reg rgb_en;
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struct vop_reg lvds_en;
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struct vop_reg edp_en;
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struct vop_reg hdmi_en;
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struct vop_reg mipi_en;
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struct vop_reg data01_swap;
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struct vop_reg mipi_dual_channel_en;
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struct vop_reg dp_en;
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struct vop_reg dclk_pol;
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struct vop_reg pin_pol;
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struct vop_reg rgb_dclk_pol;
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struct vop_reg rgb_pin_pol;
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struct vop_reg lvds_dclk_pol;
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struct vop_reg lvds_pin_pol;
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struct vop_reg hdmi_dclk_pol;
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struct vop_reg hdmi_pin_pol;
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struct vop_reg edp_dclk_pol;
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struct vop_reg edp_pin_pol;
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struct vop_reg mipi_dclk_pol;
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struct vop_reg mipi_pin_pol;
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struct vop_reg dp_dclk_pol;
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struct vop_reg dp_pin_pol;
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struct vop_reg dither_up;
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struct vop_reg dither_down;
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struct vop_reg sw_dac_sel;
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struct vop_reg tve_sw_mode;
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struct vop_reg tve_dclk_pol;
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struct vop_reg tve_dclk_en;
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struct vop_reg sw_genlock;
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struct vop_reg sw_uv_offset_en;
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struct vop_reg dsp_out_yuv;
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struct vop_reg dsp_data_swap;
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struct vop_reg dsp_ccir656_avg;
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struct vop_reg dsp_black;
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struct vop_reg dsp_blank;
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struct vop_reg dsp_outzero;
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struct vop_reg dsp_lut_en;
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struct vop_reg update_gamma_lut;
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struct vop_reg out_mode;
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struct vop_reg xmirror;
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struct vop_reg ymirror;
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struct vop_reg dsp_background;
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/* CABC */
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struct vop_reg cabc_total_num;
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struct vop_reg cabc_config_mode;
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struct vop_reg cabc_stage_up_mode;
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struct vop_reg cabc_scale_cfg_value;
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struct vop_reg cabc_scale_cfg_enable;
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struct vop_reg cabc_global_dn_limit_en;
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struct vop_reg cabc_lut_en;
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struct vop_reg cabc_en;
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struct vop_reg cabc_handle_en;
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struct vop_reg cabc_stage_up;
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struct vop_reg cabc_stage_down;
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struct vop_reg cabc_global_dn;
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struct vop_reg cabc_calc_pixel_num;
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struct vop_reg win_gate[4];
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struct vop_reg win_channel[4];
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/* BCSH */
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struct vop_reg bcsh_brightness;
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struct vop_reg bcsh_contrast;
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struct vop_reg bcsh_sat_con;
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struct vop_reg bcsh_sin_hue;
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struct vop_reg bcsh_cos_hue;
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struct vop_reg bcsh_r2y_csc_mode;
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struct vop_reg bcsh_r2y_en;
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struct vop_reg bcsh_y2r_csc_mode;
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struct vop_reg bcsh_y2r_en;
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struct vop_reg bcsh_color_bar;
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struct vop_reg bcsh_out_mode;
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struct vop_reg bcsh_en;
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struct vop_reg reg_done_frm;
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/* MCU OUTPUT */
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struct vop_reg mcu_pix_total;
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struct vop_reg mcu_cs_pst;
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struct vop_reg mcu_cs_pend;
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struct vop_reg mcu_rw_pst;
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struct vop_reg mcu_rw_pend;
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struct vop_reg mcu_clk_sel;
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struct vop_reg mcu_hold_mode;
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struct vop_reg mcu_frame_st;
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struct vop_reg mcu_rs;
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struct vop_reg mcu_bypass;
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struct vop_reg mcu_type;
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struct vop_reg mcu_rw_bypass_port;
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/* bt1120 */
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struct vop_reg bt1120_yc_swap;
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struct vop_reg bt1120_en;
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/* bt656 */
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struct vop_reg bt656_en;
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struct vop_reg cfg_done;
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};
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struct vop_scl_extension {
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struct vop_reg cbcr_vsd_mode;
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struct vop_reg cbcr_vsu_mode;
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struct vop_reg cbcr_hsd_mode;
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struct vop_reg cbcr_ver_scl_mode;
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struct vop_reg cbcr_hor_scl_mode;
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struct vop_reg yrgb_vsd_mode;
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struct vop_reg yrgb_vsu_mode;
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struct vop_reg yrgb_hsd_mode;
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struct vop_reg yrgb_ver_scl_mode;
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struct vop_reg yrgb_hor_scl_mode;
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struct vop_reg line_load_mode;
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struct vop_reg cbcr_axi_gather_num;
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struct vop_reg yrgb_axi_gather_num;
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struct vop_reg vsd_cbcr_gt2;
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struct vop_reg vsd_cbcr_gt4;
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struct vop_reg vsd_yrgb_gt2;
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struct vop_reg vsd_yrgb_gt4;
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struct vop_reg bic_coe_sel;
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struct vop_reg cbcr_axi_gather_en;
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struct vop_reg yrgb_axi_gather_en;
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struct vop_reg lb_mode;
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};
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struct vop_scl_regs {
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const struct vop_scl_extension *ext;
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struct vop_reg scale_yrgb_x;
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struct vop_reg scale_yrgb_y;
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struct vop_reg scale_cbcr_x;
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struct vop_reg scale_cbcr_y;
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};
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struct vop_win {
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const struct vop_scl_regs *scl;
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struct vop_reg gate;
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struct vop_reg enable;
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struct vop_reg format;
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struct vop_reg interlace_read;
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struct vop_reg ymirror;
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struct vop_reg rb_swap;
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struct vop_reg act_info;
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struct vop_reg dsp_info;
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struct vop_reg dsp_st;
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struct vop_reg yrgb_mst;
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struct vop_reg uv_mst;
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struct vop_reg yrgb_vir;
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struct vop_reg uv_vir;
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struct vop_reg alpha_mode;
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struct vop_reg alpha_en;
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struct vop_reg dst_alpha_ctl;
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struct vop_reg src_alpha_ctl;
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};
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struct vop_line_flag {
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struct vop_reg line_flag_num[2];
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};
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struct vop_grf_ctrl {
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struct vop_reg grf_dclk_inv;
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};
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struct vop_csc_table {
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const uint32_t *r2y_bt601;
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const uint32_t *r2y_bt601_12_235;
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const uint32_t *r2y_bt709;
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const uint32_t *r2y_bt2020;
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};
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struct vop_csc {
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struct vop_reg y2r_en;
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struct vop_reg r2r_en;
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struct vop_reg r2y_en;
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uint32_t y2r_offset;
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uint32_t r2r_offset;
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uint32_t r2y_offset;
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};
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#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
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struct vop_data {
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uint32_t version;
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const struct vop_ctrl *ctrl;
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const struct vop_win *win;
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const struct vop_line_flag *line_flag;
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const struct vop_grf_ctrl *grf_ctrl;
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const struct vop_csc_table *csc_table;
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const struct vop_csc *win_csc;
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int win_offset;
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int reg_len;
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u64 feature;
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struct vop_rect max_output;
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};
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struct vop {
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u32 *regsbak;
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void *regs;
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void *grf;
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uint32_t version;
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const struct vop_ctrl *ctrl;
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const struct vop_win *win;
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const struct vop_line_flag *line_flag;
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const struct vop_grf_ctrl *grf_ctrl;
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const struct vop_csc_table *csc_table;
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const struct vop_csc *win_csc;
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int win_offset;
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struct gpio_desc mcu_rs_gpio;
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};
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static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
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{
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writel(v, vop->regs + offset);
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vop->regsbak[offset >> 2] = v;
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}
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static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
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{
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return readl(vop->regs + offset);
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}
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static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
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const struct vop_reg *reg)
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{
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return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
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}
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static inline void vop_mask_write(struct vop *vop, uint32_t offset,
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uint32_t mask, uint32_t shift, uint32_t v,
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bool write_mask)
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{
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if (!mask)
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return;
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if (write_mask) {
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v = ((v & mask) << shift) | (mask << (shift + 16));
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} else {
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uint32_t cached_val = vop->regsbak[offset >> 2];
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v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
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vop->regsbak[offset >> 2] = v;
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}
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writel(v, vop->regs + offset);
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}
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static inline void vop_cfg_done(struct vop *vop)
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{
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VOP_CTRL_SET(vop, cfg_done, 1);
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}
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static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v)
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{
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u32 val = 0;
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if (VOP_REG_SUPPORT(vop, reg)) {
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val = (v << reg.shift) | (reg.mask << (reg.shift + 16));
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writel(val, vop->grf + reg.offset);
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}
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}
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/**
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* drm_format_horz_chroma_subsampling - get the horizontal chroma subsampling factor
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* @format: pixel format (DRM_FORMAT_*)
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*
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* Returns:
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* The horizontal chroma subsampling factor for the
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* specified pixel format.
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*/
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static inline int drm_format_horz_chroma_subsampling(uint32_t format)
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{
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/* uboot only support RGB format */
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return 1;
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}
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/**
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* drm_format_vert_chroma_subsampling - get the vertical chroma subsampling factor
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* @format: pixel format (DRM_FORMAT_*)
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*
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* Returns:
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* The vertical chroma subsampling factor for the
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* specified pixel format.
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*/
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static inline int drm_format_vert_chroma_subsampling(uint32_t format)
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{
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/* uboot only support RGB format */
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return 1;
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}
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#endif
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