/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __B4860QDS_QIXIS_H__
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#define __B4860QDS_QIXIS_H__
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/* Definitions of QIXIS Registers for B4860QDS */
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/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
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#define BRDCFG4_EMISEL_MASK 0xE0
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#define BRDCFG4_EMISEL_SHIFT 5
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/* CLK */
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#define QIXIS_CLK_66 0x0
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#define QIXIS_CLK_100 0x1
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#define QIXIS_CLK_125 0x2
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#define QIXIS_CLK_133 0x3
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#define QIXIS_SRDS1CLK_122 0x5a
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#define QIXIS_SRDS1CLK_125 0x5e
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/* SGMII */
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#define PHY_BASE_ADDR 0x18
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#define PORT_NUM 0x04
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#define REGNUM 0x00
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#endif
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