/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*/
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#ifndef _MPC8610_I2S_H
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#define _MPC8610_I2S_H
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/* -- SSI Register Map -- */
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/* SSI Transmit Data Register 0 */
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#define REG_SSI_STX0 0x00
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/* SSI Transmit Data Register 1 */
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#define REG_SSI_STX1 0x04
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/* SSI Receive Data Register 0 */
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#define REG_SSI_SRX0 0x08
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/* SSI Receive Data Register 1 */
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#define REG_SSI_SRX1 0x0c
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/* SSI Control Register */
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#define REG_SSI_SCR 0x10
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/* SSI Interrupt Status Register */
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#define REG_SSI_SISR 0x14
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/* SSI Interrupt Enable Register */
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#define REG_SSI_SIER 0x18
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/* SSI Transmit Configuration Register */
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#define REG_SSI_STCR 0x1c
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/* SSI Receive Configuration Register */
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#define REG_SSI_SRCR 0x20
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#define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
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/* SSI Transmit Clock Control Register */
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#define REG_SSI_STCCR 0x24
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/* SSI Receive Clock Control Register */
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#define REG_SSI_SRCCR 0x28
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#define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
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/* SSI FIFO Control/Status Register */
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#define REG_SSI_SFCSR 0x2c
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/*
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* SSI Test Register (Intended for debugging purposes only)
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*
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* Note: STR is not documented in recent IMX datasheet, but
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* is described in IMX51 reference manual at section 56.3.3.14
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*/
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#define REG_SSI_STR 0x30
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/*
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* SSI Option Register (Intended for internal use only)
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*
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* Note: SOR is not documented in recent IMX datasheet, but
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* is described in IMX51 reference manual at section 56.3.3.15
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*/
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#define REG_SSI_SOR 0x34
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/* SSI AC97 Control Register */
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#define REG_SSI_SACNT 0x38
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/* SSI AC97 Command Address Register */
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#define REG_SSI_SACADD 0x3c
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/* SSI AC97 Command Data Register */
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#define REG_SSI_SACDAT 0x40
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/* SSI AC97 Tag Register */
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#define REG_SSI_SATAG 0x44
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/* SSI Transmit Time Slot Mask Register */
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#define REG_SSI_STMSK 0x48
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/* SSI Receive Time Slot Mask Register */
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#define REG_SSI_SRMSK 0x4c
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#define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
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/*
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* SSI AC97 Channel Status Register
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*
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* The status could be changed by:
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* 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST
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* 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
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* 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
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*/
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#define REG_SSI_SACCST 0x50
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/* SSI AC97 Channel Enable Register -- Set bits in SACCST */
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#define REG_SSI_SACCEN 0x54
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/* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
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#define REG_SSI_SACCDIS 0x58
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/* -- SSI Register Field Maps -- */
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/* SSI Control Register -- REG_SSI_SCR 0x10 */
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#define SSI_SCR_SYNC_TX_FS 0x00001000
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#define SSI_SCR_RFR_CLK_DIS 0x00000800
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#define SSI_SCR_TFR_CLK_DIS 0x00000400
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#define SSI_SCR_TCH_EN 0x00000100
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#define SSI_SCR_SYS_CLK_EN 0x00000080
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#define SSI_SCR_I2S_MODE_MASK 0x00000060
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#define SSI_SCR_I2S_MODE_NORMAL 0x00000000
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#define SSI_SCR_I2S_MODE_MASTER 0x00000020
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#define SSI_SCR_I2S_MODE_SLAVE 0x00000040
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#define SSI_SCR_SYN 0x00000010
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#define SSI_SCR_NET 0x00000008
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#define SSI_SCR_I2S_NET_MASK (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK)
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#define SSI_SCR_RE 0x00000004
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#define SSI_SCR_TE 0x00000002
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#define SSI_SCR_SSIEN 0x00000001
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/* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
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#define SSI_SISR_RFRC 0x01000000
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#define SSI_SISR_TFRC 0x00800000
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#define SSI_SISR_CMDAU 0x00040000
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#define SSI_SISR_CMDDU 0x00020000
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#define SSI_SISR_RXT 0x00010000
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#define SSI_SISR_RDR1 0x00008000
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#define SSI_SISR_RDR0 0x00004000
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#define SSI_SISR_TDE1 0x00002000
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#define SSI_SISR_TDE0 0x00001000
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#define SSI_SISR_ROE1 0x00000800
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#define SSI_SISR_ROE0 0x00000400
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#define SSI_SISR_TUE1 0x00000200
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#define SSI_SISR_TUE0 0x00000100
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#define SSI_SISR_TFS 0x00000080
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#define SSI_SISR_RFS 0x00000040
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#define SSI_SISR_TLS 0x00000020
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#define SSI_SISR_RLS 0x00000010
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#define SSI_SISR_RFF1 0x00000008
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#define SSI_SISR_RFF0 0x00000004
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#define SSI_SISR_TFE1 0x00000002
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#define SSI_SISR_TFE0 0x00000001
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/* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
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#define SSI_SIER_RFRC_EN 0x01000000
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#define SSI_SIER_TFRC_EN 0x00800000
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#define SSI_SIER_RDMAE 0x00400000
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#define SSI_SIER_RIE 0x00200000
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#define SSI_SIER_TDMAE 0x00100000
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#define SSI_SIER_TIE 0x00080000
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#define SSI_SIER_CMDAU_EN 0x00040000
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#define SSI_SIER_CMDDU_EN 0x00020000
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#define SSI_SIER_RXT_EN 0x00010000
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#define SSI_SIER_RDR1_EN 0x00008000
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#define SSI_SIER_RDR0_EN 0x00004000
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#define SSI_SIER_TDE1_EN 0x00002000
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#define SSI_SIER_TDE0_EN 0x00001000
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#define SSI_SIER_ROE1_EN 0x00000800
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#define SSI_SIER_ROE0_EN 0x00000400
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#define SSI_SIER_TUE1_EN 0x00000200
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#define SSI_SIER_TUE0_EN 0x00000100
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#define SSI_SIER_TFS_EN 0x00000080
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#define SSI_SIER_RFS_EN 0x00000040
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#define SSI_SIER_TLS_EN 0x00000020
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#define SSI_SIER_RLS_EN 0x00000010
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#define SSI_SIER_RFF1_EN 0x00000008
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#define SSI_SIER_RFF0_EN 0x00000004
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#define SSI_SIER_TFE1_EN 0x00000002
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#define SSI_SIER_TFE0_EN 0x00000001
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/* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
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#define SSI_STCR_TXBIT0 0x00000200
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#define SSI_STCR_TFEN1 0x00000100
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#define SSI_STCR_TFEN0 0x00000080
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#define SSI_STCR_TFDIR 0x00000040
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#define SSI_STCR_TXDIR 0x00000020
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#define SSI_STCR_TSHFD 0x00000010
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#define SSI_STCR_TSCKP 0x00000008
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#define SSI_STCR_TFSI 0x00000004
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#define SSI_STCR_TFSL 0x00000002
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#define SSI_STCR_TEFS 0x00000001
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/* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
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#define SSI_SRCR_RXEXT 0x00000400
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#define SSI_SRCR_RXBIT0 0x00000200
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#define SSI_SRCR_RFEN1 0x00000100
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#define SSI_SRCR_RFEN0 0x00000080
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#define SSI_SRCR_RFDIR 0x00000040
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#define SSI_SRCR_RXDIR 0x00000020
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#define SSI_SRCR_RSHFD 0x00000010
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#define SSI_SRCR_RSCKP 0x00000008
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#define SSI_SRCR_RFSI 0x00000004
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#define SSI_SRCR_RFSL 0x00000002
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#define SSI_SRCR_REFS 0x00000001
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/*
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* SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
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* SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
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*/
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#define SSI_SxCCR_DIV2_SHIFT 18
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#define SSI_SxCCR_DIV2 0x00040000
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#define SSI_SxCCR_PSR_SHIFT 17
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#define SSI_SxCCR_PSR 0x00020000
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#define SSI_SxCCR_WL_SHIFT 13
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#define SSI_SxCCR_WL_MASK 0x0001E000
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#define SSI_SxCCR_WL(x) \
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(((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
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#define SSI_SxCCR_DC_SHIFT 8
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#define SSI_SxCCR_DC_MASK 0x00001F00
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#define SSI_SxCCR_DC(x) \
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((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
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#define SSI_SxCCR_PM_SHIFT 0
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#define SSI_SxCCR_PM_MASK 0x000000FF
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#define SSI_SxCCR_PM(x) \
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((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
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/*
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* SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
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*
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* Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
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* Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
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*/
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#define SSI_SFCSR_RFCNT1_SHIFT 28
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#define SSI_SFCSR_RFCNT1_MASK 0xF0000000
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#define SSI_SFCSR_RFCNT1(x) \
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(((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
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#define SSI_SFCSR_TFCNT1_SHIFT 24
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#define SSI_SFCSR_TFCNT1_MASK 0x0F000000
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#define SSI_SFCSR_TFCNT1(x) \
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(((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
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#define SSI_SFCSR_RFWM1_SHIFT 20
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#define SSI_SFCSR_RFWM1_MASK 0x00F00000
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#define SSI_SFCSR_RFWM1(x) \
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(((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
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#define SSI_SFCSR_TFWM1_SHIFT 16
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#define SSI_SFCSR_TFWM1_MASK 0x000F0000
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#define SSI_SFCSR_TFWM1(x) \
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(((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
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#define SSI_SFCSR_RFCNT0_SHIFT 12
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#define SSI_SFCSR_RFCNT0_MASK 0x0000F000
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#define SSI_SFCSR_RFCNT0(x) \
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(((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
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#define SSI_SFCSR_TFCNT0_SHIFT 8
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#define SSI_SFCSR_TFCNT0_MASK 0x00000F00
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#define SSI_SFCSR_TFCNT0(x) \
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(((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
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#define SSI_SFCSR_RFWM0_SHIFT 4
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#define SSI_SFCSR_RFWM0_MASK 0x000000F0
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#define SSI_SFCSR_RFWM0(x) \
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(((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
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#define SSI_SFCSR_TFWM0_SHIFT 0
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#define SSI_SFCSR_TFWM0_MASK 0x0000000F
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#define SSI_SFCSR_TFWM0(x) \
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(((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
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/* SSI Test Register -- REG_SSI_STR 0x30 */
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#define SSI_STR_TEST 0x00008000
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#define SSI_STR_RCK2TCK 0x00004000
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#define SSI_STR_RFS2TFS 0x00002000
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#define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
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#define SSI_STR_TXD2RXD 0x00000080
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#define SSI_STR_TCK2RCK 0x00000040
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#define SSI_STR_TFS2RFS 0x00000020
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#define SSI_STR_TXSTATE(x) ((x) & 0x1F)
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/* SSI Option Register -- REG_SSI_SOR 0x34 */
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#define SSI_SOR_CLKOFF 0x00000040
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#define SSI_SOR_RX_CLR 0x00000020
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#define SSI_SOR_TX_CLR 0x00000010
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#define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
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#define SSI_SOR_INIT 0x00000008
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#define SSI_SOR_WAIT_SHIFT 1
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#define SSI_SOR_WAIT_MASK 0x00000006
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#define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT)
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#define SSI_SOR_SYNRST 0x00000001
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/* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
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#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
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#define SSI_SACNT_WR 0x00000010
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#define SSI_SACNT_RD 0x00000008
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#define SSI_SACNT_RDWR_MASK 0x00000018
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#define SSI_SACNT_TIF 0x00000004
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#define SSI_SACNT_FV 0x00000002
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#define SSI_SACNT_AC97EN 0x00000001
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struct device;
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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struct fsl_ssi_dbg {
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struct dentry *dbg_dir;
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struct dentry *dbg_stats;
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struct {
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unsigned int rfrc;
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unsigned int tfrc;
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unsigned int cmdau;
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unsigned int cmddu;
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unsigned int rxt;
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unsigned int rdr1;
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unsigned int rdr0;
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unsigned int tde1;
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unsigned int tde0;
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unsigned int roe1;
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unsigned int roe0;
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unsigned int tue1;
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unsigned int tue0;
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unsigned int tfs;
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unsigned int rfs;
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unsigned int tls;
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unsigned int rls;
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unsigned int rff1;
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unsigned int rff0;
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unsigned int tfe1;
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unsigned int tfe0;
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} stats;
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};
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void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
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int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
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void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
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#else
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struct fsl_ssi_dbg {
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};
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static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
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{
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}
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static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
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struct device *dev)
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{
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return 0;
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}
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static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
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{
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}
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#endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
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#endif
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