/*
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* Copyright (c) 2018 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef __MLX5_FPGA_TLS_H__
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#define __MLX5_FPGA_TLS_H__
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#include <linux/mlx5/driver.h>
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#include <net/tls.h>
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#include "fpga/core.h"
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struct mlx5_fpga_tls {
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struct list_head pending_cmds;
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spinlock_t pending_cmds_lock; /* Protects pending_cmds */
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u32 caps;
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struct mlx5_fpga_conn *conn;
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struct idr tx_idr;
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struct idr rx_idr;
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spinlock_t tx_idr_spinlock; /* protects the IDR */
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spinlock_t rx_idr_spinlock; /* protects the IDR */
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};
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int mlx5_fpga_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
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struct tls_crypto_info *crypto_info,
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u32 start_offload_tcp_sn, u32 *p_swid,
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bool direction_sx);
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void mlx5_fpga_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
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gfp_t flags, bool direction_sx);
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bool mlx5_fpga_is_tls_device(struct mlx5_core_dev *mdev);
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int mlx5_fpga_tls_init(struct mlx5_core_dev *mdev);
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void mlx5_fpga_tls_cleanup(struct mlx5_core_dev *mdev);
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static inline u32 mlx5_fpga_tls_device_caps(struct mlx5_core_dev *mdev)
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{
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return mdev->fpga->tls->caps;
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}
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int mlx5_fpga_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
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u32 seq, __be64 rcd_sn);
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#endif /* __MLX5_FPGA_TLS_H__ */
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