Add support for RISC-V
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Upstream-Status: Pending
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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--- a/webrtc/base/basictypes.h
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+++ b/webrtc/base/basictypes.h
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@@ -29,6 +29,10 @@
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#define CPU_ARM 1
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#endif
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+#if defined(__riscv) || defined(_M_RISCV)
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+#define CPU_RISCV 1
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+#endif
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+
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#if defined(CPU_X86) && defined(CPU_ARM)
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#error CPU_X86 and CPU_ARM both defined.
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#endif
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--- a/webrtc/typedefs.h
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+++ b/webrtc/typedefs.h
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@@ -56,6 +56,13 @@
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#elif defined(__powerpc__)
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#define WEBRTC_ARCH_32_BITS
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#define WEBRTC_ARCH_BIG_ENDIAN
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+#elif defined(__riscv)
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+#if __riscv_xlen == 64
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+# define WEBRTC_ARCH_64_BITS
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+#else
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+# define WEBRTC_ARCH_32_BITS
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+#endif
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+#define WEBRTC_ARCH_LITTLE_ENDIAN
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#elif defined(__pnacl__)
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#define WEBRTC_ARCH_32_BITS
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#define WEBRTC_ARCH_LITTLE_ENDIAN
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