/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* Author: Roy Zang <tie-fei.zang@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_CORENET_SERDES_H
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#define __FSL_CORENET_SERDES_H
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enum srds_bank {
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FSL_SRDS_BANK_1 = 0,
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FSL_SRDS_BANK_2 = 1,
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FSL_SRDS_BANK_3 = 2,
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};
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int is_serdes_prtcl_valid(u32 prtcl);
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int serdes_get_lane_idx(int lane);
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int serdes_get_bank_by_lane(int lane);
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int serdes_lane_enabled(int lane);
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enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
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extern uint16_t srds_lpd_b[SRDS_MAX_BANK];
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#endif
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#endif /* __FSL_CORENET_SERDES_H */
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