/*
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* Freescale SerDes initialization routine
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*
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* Copyright 2007,2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 MontaVista Software, Inc.
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*
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* Author: Li Yang <leoli@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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/* SerDes registers */
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#define FSL_SRDSCR0_OFFS 0x0
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#define FSL_SRDSCR0_DPP_1V2 0x00008800
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#define FSL_SRDSCR0_TXEQA_MASK 0x00007000
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#define FSL_SRDSCR0_TXEQA_SATA 0x00001000
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#define FSL_SRDSCR0_TXEQE_MASK 0x00000700
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#define FSL_SRDSCR0_TXEQE_SATA 0x00000100
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#define FSL_SRDSCR1_OFFS 0x4
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#define FSL_SRDSCR1_PLLBW 0x00000040
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#define FSL_SRDSCR2_OFFS 0x8
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#define FSL_SRDSCR2_VDD_1V2 0x00800000
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#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
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#define FSL_SRDSCR2_SEIC_SATA 0x00001414
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#define FSL_SRDSCR2_SEIC_PEX 0x00001010
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#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
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#define FSL_SRDSCR3_OFFS 0xc
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#define FSL_SRDSCR3_KFR_SATA 0x10100000
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#define FSL_SRDSCR3_KPH_SATA 0x04040000
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#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
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#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
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#define FSL_SRDSCR4_OFFS 0x10
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#define FSL_SRDSCR4_PROT_SATA 0x00000808
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#define FSL_SRDSCR4_PROT_PEX 0x00000101
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#define FSL_SRDSCR4_PROT_SGMII 0x00000505
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#define FSL_SRDSCR4_PLANE_X2 0x01000000
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#define FSL_SRDSRSTCTL_OFFS 0x20
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#define FSL_SRDSRSTCTL_RST 0x80000000
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#define FSL_SRDSRSTCTL_SATA_RESET 0xf
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void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
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{
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void *regs = (void *)CONFIG_SYS_IMMR + offset;
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u32 tmp;
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/* 1.0V corevdd */
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if (vdd) {
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/* DPPE/DPPA = 0 */
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tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
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tmp &= ~FSL_SRDSCR0_DPP_1V2;
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out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
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/* VDD = 0 */
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tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_VDD_1V2;
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out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
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}
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/* protocol specific configuration */
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switch (proto) {
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case FSL_SERDES_PROTO_SATA:
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/* Set and clear reset bits */
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tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
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tmp |= FSL_SRDSRSTCTL_SATA_RESET;
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out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
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udelay(1000);
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tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
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out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
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/* Configure SRDSCR0 */
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clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
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FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
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FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
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/* Configure SRDSCR1 */
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tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_PLLBW;
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out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
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/* Configure SRDSCR2 */
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tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_SEIC_MASK;
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tmp |= FSL_SRDSCR2_SEIC_SATA;
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out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
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/* Configure SRDSCR3 */
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tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
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FSL_SRDSCR3_SDFM_SATA_PEX |
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FSL_SRDSCR3_SDTXL_SATA;
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out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
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/* Configure SRDSCR4 */
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tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
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out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
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break;
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case FSL_SERDES_PROTO_PEX:
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case FSL_SERDES_PROTO_PEX_X2:
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/* Configure SRDSCR1 */
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tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
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tmp |= FSL_SRDSCR1_PLLBW;
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out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
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/* Configure SRDSCR2 */
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tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_SEIC_MASK;
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tmp |= FSL_SRDSCR2_SEIC_PEX;
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out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
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/* Configure SRDSCR3 */
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tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
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out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
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/* Configure SRDSCR4 */
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tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
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if (proto == FSL_SERDES_PROTO_PEX_X2)
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tmp |= FSL_SRDSCR4_PLANE_X2;
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out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
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break;
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case FSL_SERDES_PROTO_SGMII:
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/* Configure SRDSCR1 */
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tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_PLLBW;
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out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
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/* Configure SRDSCR2 */
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tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_SEIC_MASK;
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tmp |= FSL_SRDSCR2_SEIC_SGMII;
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out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
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/* Configure SRDSCR3 */
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out_be32(regs + FSL_SRDSCR3_OFFS, 0);
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/* Configure SRDSCR4 */
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tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
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out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
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break;
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default:
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return;
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}
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/* Do a software reset */
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tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
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tmp |= FSL_SRDSRSTCTL_RST;
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out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
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}
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