// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2016 Realtek Corporation.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../mp_precomp.h"
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#include "../phydm_precomp.h"
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static void phydm_dynamic_switch_htstf_mumimo_8822b(struct phy_dm_struct *dm)
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{
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/*if rssi > 40dBm, enable HT-STF gain controller,
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*otherwise, if rssi < 40dBm, disable the controller
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*/
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/*add by Chun-Hung Ho 20160711 */
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if (dm->rssi_min >= 40)
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odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x1);
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else if (dm->rssi_min < 35)
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odm_set_bb_reg(dm, 0x8d8, BIT(17), 0x0);
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ODM_RT_TRACE(dm, ODM_COMP_COMMON, "%s, rssi_min = %d\n", __func__,
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dm->rssi_min);
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}
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static void _set_tx_a_cali_value(struct phy_dm_struct *dm, u8 rf_path,
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u8 offset, u8 tx_a_bias_offset)
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{
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u32 modi_tx_a_value = 0;
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u8 tmp1_byte = 0;
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bool is_minus = false;
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u8 comp_value = 0;
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switch (offset) {
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case 0x0:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10124);
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break;
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case 0x1:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10524);
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break;
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case 0x2:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10924);
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break;
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case 0x3:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X10D24);
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break;
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case 0x4:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30164);
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break;
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case 0x5:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30564);
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break;
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case 0x6:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30964);
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break;
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case 0x7:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X30D64);
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break;
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case 0x8:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50195);
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break;
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case 0x9:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50595);
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break;
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case 0xa:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50995);
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break;
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case 0xb:
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odm_set_rf_reg(dm, rf_path, 0x18, 0xFFFFF, 0X50D95);
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break;
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default:
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ODM_RT_TRACE(dm, ODM_COMP_COMMON,
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"Invalid TxA band offset...\n");
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return;
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}
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/* Get TxA value */
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modi_tx_a_value = odm_get_rf_reg(dm, rf_path, 0x61, 0xFFFFF);
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tmp1_byte = (u8)modi_tx_a_value & (BIT(3) | BIT(2) | BIT(1) | BIT(0));
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/* check how much need to calibration */
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switch (tx_a_bias_offset) {
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case 0xF6:
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is_minus = true;
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comp_value = 3;
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break;
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case 0xF4:
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is_minus = true;
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comp_value = 2;
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break;
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case 0xF2:
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is_minus = true;
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comp_value = 1;
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break;
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case 0xF3:
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is_minus = false;
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comp_value = 1;
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break;
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case 0xF5:
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is_minus = false;
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comp_value = 2;
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break;
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case 0xF7:
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is_minus = false;
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comp_value = 3;
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break;
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case 0xF9:
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is_minus = false;
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comp_value = 4;
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break;
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/* do nothing case */
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case 0xF0:
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default:
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ODM_RT_TRACE(dm, ODM_COMP_COMMON,
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"No need to do TxA bias current calibration\n");
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return;
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}
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/* calc correct value to calibrate */
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if (is_minus) {
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if (tmp1_byte >= comp_value) {
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tmp1_byte -= comp_value;
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/*modi_tx_a_value += tmp1_byte;*/
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} else {
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tmp1_byte = 0;
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}
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} else {
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tmp1_byte += comp_value;
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if (tmp1_byte >= 7)
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tmp1_byte = 7;
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}
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/* Write back to RF reg */
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odm_set_rf_reg(dm, rf_path, 0x30, 0xFFFF,
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(offset << 12 | (modi_tx_a_value & 0xFF0) | tmp1_byte));
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}
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static void _txa_bias_cali_4_each_path(struct phy_dm_struct *dm, u8 rf_path,
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u8 efuse_value)
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{
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/* switch on set TxA bias */
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odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x200);
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/* Set 12 sets of TxA value */
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_set_tx_a_cali_value(dm, rf_path, 0x0, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x1, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x2, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x3, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x4, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x5, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x6, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x7, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x8, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0x9, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0xa, efuse_value);
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_set_tx_a_cali_value(dm, rf_path, 0xb, efuse_value);
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/* switch off set TxA bias */
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odm_set_rf_reg(dm, rf_path, 0xEF, 0xFFFFF, 0x0);
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}
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/*
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* for 8822B PCIE D-cut patch only
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* Normal driver and MP driver need this patch
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*/
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void phydm_txcurrentcalibration(struct phy_dm_struct *dm)
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{
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u8 efuse0x3D8, efuse0x3D7;
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u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0;
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/* save original 0x18 value */
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orig_rf0x18_path_a = odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF);
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orig_rf0x18_path_b = odm_get_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF);
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/* define efuse content */
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efuse0x3D8 = dm->efuse0x3d8;
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efuse0x3D7 = dm->efuse0x3d7;
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/* check efuse content to judge whether need to calibration or not */
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if (efuse0x3D7 == 0xFF) {
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ODM_RT_TRACE(
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dm, ODM_COMP_COMMON,
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"efuse content 0x3D7 == 0xFF, No need to do TxA cali\n");
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return;
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}
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/* write RF register for calibration */
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_txa_bias_cali_4_each_path(dm, ODM_RF_PATH_A, efuse0x3D7);
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_txa_bias_cali_4_each_path(dm, ODM_RF_PATH_B, efuse0x3D8);
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/* restore original 0x18 value */
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odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xFFFFF, orig_rf0x18_path_a);
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odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x18, 0xFFFFF, orig_rf0x18_path_b);
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}
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void phydm_hwsetting_8822b(struct phy_dm_struct *dm)
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{
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phydm_dynamic_switch_htstf_mumimo_8822b(dm);
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}
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