/*************************************************************************/ /*!
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@File rgx_fwif.h
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@Title RGX firmware interface structures
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description RGX firmware interface structures used by srvinit and server
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined (__RGX_FWIF_H__)
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#define __RGX_FWIF_H__
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#include "rgx_firmware_processor.h"
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#include "rgx_fwif_shared.h"
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/*************************************************************************/ /*!
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Logging type
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*/ /**************************************************************************/
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#define RGXFWIF_LOG_TYPE_NONE 0x00000000
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#define RGXFWIF_LOG_TYPE_TRACE 0x00000001
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#define RGXFWIF_LOG_TYPE_GROUP_MAIN 0x00000002
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#define RGXFWIF_LOG_TYPE_GROUP_MTS 0x00000004
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#define RGXFWIF_LOG_TYPE_GROUP_CLEANUP 0x00000008
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#define RGXFWIF_LOG_TYPE_GROUP_CSW 0x00000010
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#define RGXFWIF_LOG_TYPE_GROUP_BIF 0x00000020
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#define RGXFWIF_LOG_TYPE_GROUP_PM 0x00000040
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#define RGXFWIF_LOG_TYPE_GROUP_RTD 0x00000080
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#define RGXFWIF_LOG_TYPE_GROUP_SPM 0x00000100
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#define RGXFWIF_LOG_TYPE_GROUP_POW 0x00000200
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#define RGXFWIF_LOG_TYPE_GROUP_HWR 0x00000400
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#define RGXFWIF_LOG_TYPE_GROUP_HWP 0x00000800
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#define RGXFWIF_LOG_TYPE_GROUP_RPM 0x00001000
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#define RGXFWIF_LOG_TYPE_GROUP_DMA 0x00002000
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#define RGXFWIF_LOG_TYPE_GROUP_DEBUG 0x80000000
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#define RGXFWIF_LOG_TYPE_GROUP_MASK 0x80003FFE
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#define RGXFWIF_LOG_TYPE_MASK 0x80003FFF
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/* String used in pvrdebug -h output */
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#define RGXFWIF_LOG_GROUPS_STRING_LIST "main,mts,cleanup,csw,bif,pm,rtd,spm,pow,hwr,hwp,rpm,dma,debug"
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/* Table entry to map log group strings to log type value */
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typedef struct {
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const IMG_CHAR* pszLogGroupName;
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IMG_UINT32 ui32LogGroupType;
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} RGXFWIF_LOG_GROUP_MAP_ENTRY;
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/*
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Macro for use with the RGXFWIF_LOG_GROUP_MAP_ENTRY type to create a lookup
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table where needed. Keep log group names short, no more than 20 chars.
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*/
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#define RGXFWIF_LOG_GROUP_NAME_VALUE_MAP { "none", RGXFWIF_LOG_TYPE_NONE }, \
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{ "main", RGXFWIF_LOG_TYPE_GROUP_MAIN }, \
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{ "mts", RGXFWIF_LOG_TYPE_GROUP_MTS }, \
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{ "cleanup", RGXFWIF_LOG_TYPE_GROUP_CLEANUP }, \
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{ "csw", RGXFWIF_LOG_TYPE_GROUP_CSW }, \
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{ "bif", RGXFWIF_LOG_TYPE_GROUP_BIF }, \
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{ "pm", RGXFWIF_LOG_TYPE_GROUP_PM }, \
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{ "rtd", RGXFWIF_LOG_TYPE_GROUP_RTD }, \
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{ "spm", RGXFWIF_LOG_TYPE_GROUP_SPM }, \
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{ "pow", RGXFWIF_LOG_TYPE_GROUP_POW }, \
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{ "hwr", RGXFWIF_LOG_TYPE_GROUP_HWR }, \
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{ "hwp", RGXFWIF_LOG_TYPE_GROUP_HWP }, \
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{ "rpm", RGXFWIF_LOG_TYPE_GROUP_RPM }, \
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{ "dma", RGXFWIF_LOG_TYPE_GROUP_DMA }, \
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{ "debug", RGXFWIF_LOG_TYPE_GROUP_DEBUG }
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/* Used in print statements to display log group state, one %s per group defined */
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#define RGXFWIF_LOG_ENABLED_GROUPS_LIST_PFSPEC "%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
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/* Used in a print statement to display log group state, one per group */
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#define RGXFWIF_LOG_ENABLED_GROUPS_LIST(types) (((types) & RGXFWIF_LOG_TYPE_GROUP_MAIN) ?("main ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_MTS) ?("mts ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_CLEANUP) ?("cleanup ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_CSW) ?("csw ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_BIF) ?("bif ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_PM) ?("pm ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_RTD) ?("rtd ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_SPM) ?("spm ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_POW) ?("pow ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_HWR) ?("hwr ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_HWP) ?("hwp ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_RPM) ?("rpm ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_DMA) ?("dma ") :("")), \
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(((types) & RGXFWIF_LOG_TYPE_GROUP_DEBUG) ?("debug ") :(""))
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/*! Logging function */
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typedef void (*PFN_RGXFW_LOG) (const IMG_CHAR* pszFmt, ...);
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/************************************************************************
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* RGX FW signature checks
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************************************************************************/
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#define RGXFW_SIG_BUFFER_SIZE_MIN (1024)
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/*!
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******************************************************************************
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* HWPERF
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*****************************************************************************/
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/* Size of the Firmware L1 HWPERF buffer in bytes (2MB). Accessed by the
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* Firmware and host driver. */
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#define RGXFW_HWPERF_L1_SIZE_MIN (16U)
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#define RGXFW_HWPERF_L1_SIZE_DEFAULT (2048U)
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#define RGXFW_HWPERF_L1_SIZE_MAX (12288U)
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/* This padding value must always be large enough to hold the biggest
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* variable sized packet. */
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#define RGXFW_HWPERF_L1_PADDING_DEFAULT (RGX_HWPERF_MAX_PACKET_SIZE)
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/*!
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******************************************************************************
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* Trace Buffer
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*****************************************************************************/
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/*! Number of elements on each line when dumping the trace buffer */
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#define RGXFW_TRACE_BUFFER_LINESIZE (30)
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/*! Total size of RGXFWIF_TRACEBUF dword (needs to be a multiple of RGXFW_TRACE_BUFFER_LINESIZE) */
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#define RGXFW_TRACE_BUFFER_SIZE (400*RGXFW_TRACE_BUFFER_LINESIZE)
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#define RGXFW_TRACE_BUFFER_ASSERT_SIZE 200
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#if defined(RGXFW_META_SUPPORT_2ND_THREAD)
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#define RGXFW_THREAD_NUM 2
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#else
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#define RGXFW_THREAD_NUM 1
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#endif
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#define RGXFW_POLL_TYPE_SET 0x80000000
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typedef struct _RGXFWIF_ASSERTBUF_
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{
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IMG_CHAR szPath[RGXFW_TRACE_BUFFER_ASSERT_SIZE];
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IMG_CHAR szInfo[RGXFW_TRACE_BUFFER_ASSERT_SIZE];
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IMG_UINT32 ui32LineNum;
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} UNCACHED_ALIGN RGXFWIF_ASSERTBUF;
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typedef struct _RGXFWIF_TRACEBUF_SPACE_
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{
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IMG_UINT32 ui32TracePointer;
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#if defined (RGX_FIRMWARE)
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IMG_UINT32 *pui32RGXFWIfTraceBuffer; /* To be used by firmware for writing into trace buffer */
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#else
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RGXFWIF_DEV_VIRTADDR pui32RGXFWIfTraceBuffer;
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#endif
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IMG_PUINT32 pui32TraceBuffer; /* To be used by host when reading from trace buffer */
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RGXFWIF_ASSERTBUF sAssertBuf;
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} UNCACHED_ALIGN RGXFWIF_TRACEBUF_SPACE;
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#define RGXFWIF_POW_STATES \
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X(RGXFWIF_POW_OFF) /* idle and handshaked with the host (ready to full power down) */ \
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X(RGXFWIF_POW_ON) /* running HW mds */ \
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X(RGXFWIF_POW_FORCED_IDLE) /* forced idle */ \
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X(RGXFWIF_POW_IDLE) /* idle waiting for host handshake */
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typedef enum _RGXFWIF_POW_STATE_
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{
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#define X(NAME) NAME,
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RGXFWIF_POW_STATES
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#undef X
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} RGXFWIF_POW_STATE;
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/* Firmware HWR states */
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#define RGXFWIF_HWR_HARDWARE_OK (0x1 << 0) /*!< Tells if the HW state is ok or locked up */
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#define RGXFWIF_HWR_ANALYSIS_DONE (0x1 << 2) /*!< Tells if the analysis of a GPU lockup has already been performed */
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#define RGXFWIF_HWR_GENERAL_LOCKUP (0x1 << 3) /*!< Tells if a DM unrelated lockup has been detected */
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#define RGXFWIF_HWR_DM_RUNNING_OK (0x1 << 4) /*!< Tells if at least one DM is running without being close to a lockup */
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#define RGXFWIF_HWR_DM_STALLING (0x1 << 5) /*!< Tells if at least one DM is close to lockup */
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typedef IMG_UINT32 RGXFWIF_HWR_STATEFLAGS;
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/* Firmware per-DM HWR states */
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#define RGXFWIF_DM_STATE_WORKING (0x00) /*!< DM is working if all flags are cleared */
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#define RGXFWIF_DM_STATE_READY_FOR_HWR (0x1 << 0) /*!< DM is idle and ready for HWR */
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#define RGXFWIF_DM_STATE_NEEDS_SKIP (0x1 << 2) /*!< DM need to skip to next cmd before resuming processing */
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#define RGXFWIF_DM_STATE_NEEDS_PR_CLEANUP (0x1 << 3) /*!< DM need partial render cleanup before resuming processing */
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#define RGXFWIF_DM_STATE_NEEDS_TRACE_CLEAR (0x1 << 4) /*!< DM need to increment Recovery Count once fully recovered */
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#define RGXFWIF_DM_STATE_GUILTY_LOCKUP (0x1 << 5) /*!< DM was identified as locking up and causing HWR */
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#define RGXFWIF_DM_STATE_INNOCENT_LOCKUP (0x1 << 6) /*!< DM was innocently affected by another lockup which caused HWR */
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#define RGXFWIF_DM_STATE_GUILTY_OVERRUNING (0x1 << 7) /*!< DM was identified as over-running and causing HWR */
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#define RGXFWIF_DM_STATE_INNOCENT_OVERRUNING (0x1 << 8) /*!< DM was innocently affected by another DM over-running which caused HWR */
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/* Per-OSid States */
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#define RGXFW_OS_STATE_ACTIVE_OS (1 << 0) /*!< Non active operating systems should not be served by the FW */
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#define RGXFW_OS_STATE_FREELIST_OK (1 << 1) /*!< Pending freelist reconstruction from that particular OS */
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#define RGXFW_OS_STATE_OFFLOADING (1 << 2) /*!< Transient state while all the OS resources in the FW are cleaned up */
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#define RGXFW_OS_STATE_GROW_REQUEST_PENDING (1 << 3) /*!< Signifies whether a request to grow a freelist is pending completion */
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typedef IMG_UINT32 RGXFWIF_HWR_RECOVERYFLAGS;
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typedef struct _RGXFWIF_TRACEBUF_
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{
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IMG_UINT32 ui32LogType;
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volatile RGXFWIF_POW_STATE ePowState;
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RGXFWIF_TRACEBUF_SPACE sTraceBuf[RGXFW_THREAD_NUM];
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IMG_UINT32 aui32HwrDmLockedUpCount[RGXFWIF_DM_DEFAULT_MAX];
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IMG_UINT32 aui32HwrDmOverranCount[RGXFWIF_DM_DEFAULT_MAX];
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IMG_UINT32 aui32HwrDmRecoveredCount[RGXFWIF_DM_DEFAULT_MAX];
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IMG_UINT32 aui32HwrDmFalseDetectCount[RGXFWIF_DM_DEFAULT_MAX];
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IMG_UINT32 ui32HwrCounter;
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IMG_UINT32 aui32CrPollAddr[RGXFW_THREAD_NUM];
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IMG_UINT32 aui32CrPollMask[RGXFW_THREAD_NUM];
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RGXFWIF_HWR_STATEFLAGS ui32HWRStateFlags;
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RGXFWIF_HWR_RECOVERYFLAGS aui32HWRRecoveryFlags[RGXFWIF_DM_DEFAULT_MAX];
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volatile IMG_UINT32 ui32HWPerfRIdx;
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volatile IMG_UINT32 ui32HWPerfWIdx;
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volatile IMG_UINT32 ui32HWPerfWrapCount;
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IMG_UINT32 ui32HWPerfSize; /* Constant after setup, needed in FW */
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IMG_UINT32 ui32HWPerfDropCount; /* The number of times the FW drops a packet due to buffer full */
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/* These next three items are only valid at runtime when the FW is built
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* with RGX_HWPERF_UTILIZATION & RGX_HWPERF_DROP_TRACKING defined
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* in rgxfw_hwperf.c */
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IMG_UINT32 ui32HWPerfUt; /* Buffer utilisation, high watermark of bytes in use */
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IMG_UINT32 ui32FirstDropOrdinal;/* The ordinal of the first packet the FW dropped */
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IMG_UINT32 ui32LastDropOrdinal; /* The ordinal of the last packet the FW dropped */
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volatile IMG_UINT32 aui32InterruptCount[RGXFW_THREAD_NUM]; /*!< Interrupt count from Threads > */
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IMG_UINT32 ui32KCCBCmdsExecuted;
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IMG_UINT64 RGXFW_ALIGN ui64StartIdleTime;
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IMG_UINT32 ui32PowMonEnergy; /* Non-volatile power monitor energy count */
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#define RGXFWIF_MAX_PCX 16
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IMG_UINT32 ui32T1PCX[RGXFWIF_MAX_PCX];
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IMG_UINT32 ui32T1PCXWOff;
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IMG_UINT32 ui32OSStateFlags[RGXFW_NUM_OS]; /*!< State flags for each Operating System > */
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IMG_UINT32 ui32MMUFlushCounter;
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} UNCACHED_ALIGN RGXFWIF_TRACEBUF;
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/*!
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******************************************************************************
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* GPU Utilisation
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*****************************************************************************/
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#define RGXFWIF_GPU_STATS_MAX_VALUE_OF_STATE 10000
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#define RGXFWIF_GPU_UTIL_STATE_ACTIVE_LOW (0U)
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#define RGXFWIF_GPU_UTIL_STATE_IDLE (1U)
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#define RGXFWIF_GPU_UTIL_STATE_ACTIVE_HIGH (2U)
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#define RGXFWIF_GPU_UTIL_STATE_BLOCKED (3U)
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#define RGXFWIF_GPU_UTIL_STATE_NUM (4U)
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#define RGXFWIF_GPU_UTIL_TIME_MASK IMG_UINT64_C(0xFFFFFFFFFFFFFFFC)
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#define RGXFWIF_GPU_UTIL_STATE_MASK IMG_UINT64_C(0x0000000000000003)
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#define RGXFWIF_GPU_UTIL_GET_TIME(word) ((word) & RGXFWIF_GPU_UTIL_TIME_MASK)
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#define RGXFWIF_GPU_UTIL_GET_STATE(word) ((word) & RGXFWIF_GPU_UTIL_STATE_MASK)
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/* The OS timestamps computed by the FW are approximations of the real time,
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* which means they could be slightly behind or ahead the real timer on the Host.
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* In some cases we can perform subtractions between FW approximated
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* timestamps and real OS timestamps, so we need a form of protection against
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* negative results if for instance the FW one is a bit ahead of time.
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*/
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#define RGXFWIF_GPU_UTIL_GET_PERIOD(newtime,oldtime) \
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((newtime) > (oldtime) ? ((newtime) - (oldtime)) : 0)
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#define RGXFWIF_GPU_UTIL_MAKE_WORD(time,state) \
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(RGXFWIF_GPU_UTIL_GET_TIME(time) | RGXFWIF_GPU_UTIL_GET_STATE(state))
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/* The timer correlation array must be big enough to ensure old entries won't be
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* overwritten before all the HWPerf events linked to those entries are processed
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* by the MISR. The update frequency of this array depends on how fast the system
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* can change state (basically how small the APM latency is) and perform DVFS transitions.
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*
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* The minimum size is 2 (not 1) to avoid race conditions between the FW reading
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* an entry while the Host is updating it. With 2 entries in the worst case the FW
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* will read old data, which is still quite ok if the Host is updating the timer
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* correlation at that time.
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*/
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#define RGXFWIF_TIME_CORR_ARRAY_SIZE 256
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#define RGXFWIF_TIME_CORR_CURR_INDEX(seqcount) ((seqcount) % RGXFWIF_TIME_CORR_ARRAY_SIZE)
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/* Make sure the timer correlation array size is a power of 2 */
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static_assert((RGXFWIF_TIME_CORR_ARRAY_SIZE & (RGXFWIF_TIME_CORR_ARRAY_SIZE - 1)) == 0,
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"RGXFWIF_TIME_CORR_ARRAY_SIZE must be a power of two");
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typedef struct _RGXFWIF_GPU_UTIL_FWCB_
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{
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RGXFWIF_TIME_CORR sTimeCorr[RGXFWIF_TIME_CORR_ARRAY_SIZE];
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IMG_UINT32 ui32TimeCorrSeqCount;
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/* Last GPU state + OS time of the last state update */
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IMG_UINT64 RGXFW_ALIGN ui64LastWord;
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/* Counters for the amount of time the GPU was active/idle/blocked */
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IMG_UINT64 RGXFW_ALIGN aui64StatsCounters[RGXFWIF_GPU_UTIL_STATE_NUM];
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} UNCACHED_ALIGN RGXFWIF_GPU_UTIL_FWCB;
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/*!
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******************************************************************************
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* HWR Data
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*****************************************************************************/
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typedef enum _RGX_HWRTYPE_
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{
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RGX_HWRTYPE_UNKNOWNFAILURE = 0,
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RGX_HWRTYPE_OVERRUN = 1,
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RGX_HWRTYPE_POLLFAILURE = 2,
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RGX_HWRTYPE_BIF0FAULT = 3,
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RGX_HWRTYPE_BIF1FAULT = 4,
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RGX_HWRTYPE_TEXASBIF0FAULT = 5,
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RGX_HWRTYPE_DPXMMUFAULT = 6,
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RGX_HWRTYPE_MMUFAULT = 7,
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RGX_HWRTYPE_MMUMETAFAULT = 8,
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} RGX_HWRTYPE;
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#define RGXFWIF_HWRTYPE_BIF_BANK_GET(eHWRType) ((eHWRType == RGX_HWRTYPE_BIF0FAULT) ? 0 : 1 )
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#define RGXFWIF_HWRTYPE_PAGE_FAULT_GET(eHWRType) ((eHWRType == RGX_HWRTYPE_BIF0FAULT || \
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eHWRType == RGX_HWRTYPE_BIF1FAULT || \
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eHWRType == RGX_HWRTYPE_TEXASBIF0FAULT || \
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eHWRType == RGX_HWRTYPE_MMUFAULT || \
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eHWRType == RGX_HWRTYPE_MMUMETAFAULT) ? 1 : 0 )
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typedef struct _RGX_BIFINFO_
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{
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IMG_UINT64 RGXFW_ALIGN ui64BIFReqStatus;
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IMG_UINT64 RGXFW_ALIGN ui64BIFMMUStatus;
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IMG_UINT64 RGXFW_ALIGN ui64PCAddress; /*!< phys address of the page catalogue */
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} RGX_BIFINFO;
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typedef struct _RGX_MMUINFO_
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{
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IMG_UINT64 RGXFW_ALIGN ui64MMUStatus;
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IMG_UINT64 RGXFW_ALIGN ui64PCAddress; /*!< phys address of the page catalogue */
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} RGX_MMUINFO;
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typedef struct _RGX_POLLINFO_
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{
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IMG_UINT32 ui32ThreadNum;
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IMG_UINT32 ui32CrPollAddr;
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IMG_UINT32 ui32CrPollMask;
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} UNCACHED_ALIGN RGX_POLLINFO;
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typedef struct _RGX_HWRINFO_
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{
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union
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{
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RGX_BIFINFO sBIFInfo;
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RGX_MMUINFO sMMUInfo;
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RGX_POLLINFO sPollInfo;
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} uHWRData;
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IMG_UINT64 RGXFW_ALIGN ui64CRTimer;
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IMG_UINT64 RGXFW_ALIGN ui64OSTimer;
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IMG_UINT32 ui32FrameNum;
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IMG_UINT32 ui32PID;
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IMG_UINT32 ui32ActiveHWRTData;
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IMG_UINT32 ui32HWRNumber;
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IMG_UINT32 ui32EventStatus;
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IMG_UINT32 ui32HWRRecoveryFlags;
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RGX_HWRTYPE eHWRType;
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RGXFWIF_DM eDM;
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IMG_UINT64 RGXFW_ALIGN ui64CRTimeOfKick;
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IMG_UINT64 RGXFW_ALIGN ui64CRTimeHWResetStart;
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IMG_UINT64 RGXFW_ALIGN ui64CRTimeHWResetFinish;
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IMG_UINT64 RGXFW_ALIGN ui64CRTimeFreelistReady;
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} UNCACHED_ALIGN RGX_HWRINFO;
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#define RGXFWIF_HWINFO_MAX_FIRST 8 /* Number of first HWR logs recorded (never overwritten by newer logs) */
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#define RGXFWIF_HWINFO_MAX_LAST 8 /* Number of latest HWR logs (older logs are overwritten by newer logs) */
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#define RGXFWIF_HWINFO_MAX (RGXFWIF_HWINFO_MAX_FIRST + RGXFWIF_HWINFO_MAX_LAST) /* Total number of HWR logs stored in a buffer */
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#define RGXFWIF_HWINFO_LAST_INDEX (RGXFWIF_HWINFO_MAX - 1) /* Index of the last log in the HWR log buffer */
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typedef struct _RGXFWIF_HWRINFOBUF_
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{
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RGX_HWRINFO sHWRInfo[RGXFWIF_HWINFO_MAX];
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IMG_UINT32 ui32FirstCrPollAddr[RGXFW_THREAD_NUM];
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IMG_UINT32 ui32FirstCrPollMask[RGXFW_THREAD_NUM];
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IMG_UINT32 ui32WriteIndex;
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IMG_UINT32 ui32DDReqCount;
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} UNCACHED_ALIGN RGXFWIF_HWRINFOBUF;
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#define RGXFWIF_CTXSWITCH_PROFILE_FAST_EN (1)
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#define RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN (2)
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#define RGXFWIF_CTXSWITCH_PROFILE_SLOW_EN (3)
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#define RGXFWIF_CTXSWITCH_PROFILE_NODELAY_EN (4)
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/*!
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******************************************************************************
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* RGX firmware Init Config Data
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*****************************************************************************/
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#define RGXFWIF_INICFG_CTXSWITCH_TA_EN (0x1 << 0)
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#define RGXFWIF_INICFG_CTXSWITCH_3D_EN (0x1 << 1)
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#define RGXFWIF_INICFG_CTXSWITCH_CDM_EN (0x1 << 2)
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#define RGXFWIF_INICFG_CTXSWITCH_MODE_RAND (0x1 << 3)
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#define RGXFWIF_INICFG_CTXSWITCH_SRESET_EN (0x1 << 4)
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#define RGXFWIF_INICFG_RSVD (0x1 << 5)
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#define RGXFWIF_INICFG_POW_RASCALDUST (0x1 << 6)
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#define RGXFWIF_INICFG_HWPERF_EN (0x1 << 7)
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#define RGXFWIF_INICFG_HWR_EN (0x1 << 8)
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#define RGXFWIF_INICFG_CHECK_MLIST_EN (0x1 << 9)
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#define RGXFWIF_INICFG_DISABLE_CLKGATING_EN (0x1 << 10)
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#define RGXFWIF_INICFG_POLL_COUNTERS_EN (0x1 << 11)
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#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INDEX (RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX << 12)
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#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_INSTANCE (RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE << 12)
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#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_LIST (RGX_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST << 12)
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#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_CLRMSK (0xFFFFCFFFU)
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#define RGXFWIF_INICFG_VDM_CTX_STORE_MODE_SHIFT (12)
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#define RGXFWIF_INICFG_SHG_BYPASS_EN (0x1 << 14)
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#define RGXFWIF_INICFG_RTU_BYPASS_EN (0x1 << 15)
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#define RGXFWIF_INICFG_REGCONFIG_EN (0x1 << 16)
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#define RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY (0x1 << 17)
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#define RGXFWIF_INICFG_HWP_DISABLE_FILTER (0x1 << 18)
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#define RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN (0x1 << 19)
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#define RGXFWIF_INICFG_CDM_KILL_MODE_RAND_EN (0x1 << 20)
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#define RGXFWIF_INICFG_DISABLE_DM_OVERLAP (0x1 << 21)
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#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT (22)
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#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_FAST (RGXFWIF_CTXSWITCH_PROFILE_FAST_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
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#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MEDIUM (RGXFWIF_CTXSWITCH_PROFILE_MEDIUM_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
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#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_SLOW (RGXFWIF_CTXSWITCH_PROFILE_SLOW_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
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#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_NODELAY (RGXFWIF_CTXSWITCH_PROFILE_NODELAY_EN << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
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#define RGXFWIF_INICFG_CTXSWITCH_PROFILE_MASK (0x7 << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT)
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#define RGXFWIF_INICFG_METAT1_SHIFT (25)
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#define RGXFWIF_INICFG_METAT1_MAIN (RGX_META_T1_MAIN << RGXFWIF_INICFG_METAT1_SHIFT)
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#define RGXFWIF_INICFG_METAT1_DUMMY (RGX_META_T1_DUMMY << RGXFWIF_INICFG_METAT1_SHIFT)
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#define RGXFWIF_INICFG_METAT1_ENABLED (RGXFWIF_INICFG_METAT1_MAIN | RGXFWIF_INICFG_METAT1_DUMMY)
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#define RGXFWIF_INICFG_METAT1_MASK (RGXFWIF_INICFG_METAT1_ENABLED >> RGXFWIF_INICFG_METAT1_SHIFT)
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#define RGXFWIF_INICFG_ASSERT_ON_HWR_TRIGGER (0x1 << 27)
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#define RGXFWIF_INICFG_WORKEST_V1 (0x1 << 28)
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#define RGXFWIF_INICFG_WORKEST_V2 (0x1 << 29)
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#define RGXFWIF_INICFG_PDVFS_V1 (0x1 << 30)
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#define RGXFWIF_INICFG_PDVFS_V2 (0x1 << 31)
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#define RGXFWIF_INICFG_ALL (0xFFFFFFDFU)
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#define RGXFWIF_SRVCFG_DISABLE_PDP_EN (0x1 << 31)
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#define RGXFWIF_SRVCFG_ALL (0x80000000U)
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#define RGXFWIF_FILTCFG_TRUNCATE_HALF (0x1 << 3)
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#define RGXFWIF_FILTCFG_TRUNCATE_INT (0x1 << 2)
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#define RGXFWIF_FILTCFG_NEW_FILTER_MODE (0x1 << 1)
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#define RGXFWIF_INICFG_CTXSWITCH_DM_ALL (RGXFWIF_INICFG_CTXSWITCH_TA_EN | \
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RGXFWIF_INICFG_CTXSWITCH_3D_EN | \
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RGXFWIF_INICFG_CTXSWITCH_CDM_EN)
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#define RGXFWIF_INICFG_CTXSWITCH_CLRMSK ~(RGXFWIF_INICFG_CTXSWITCH_DM_ALL | \
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RGXFWIF_INICFG_CTXSWITCH_MODE_RAND | \
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RGXFWIF_INICFG_CTXSWITCH_SRESET_EN)
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typedef enum
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{
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RGX_ACTIVEPM_FORCE_OFF = 0,
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RGX_ACTIVEPM_FORCE_ON = 1,
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RGX_ACTIVEPM_DEFAULT = 2
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} RGX_ACTIVEPM_CONF;
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typedef enum
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{
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RGX_RD_POWER_ISLAND_FORCE_OFF = 0,
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RGX_RD_POWER_ISLAND_FORCE_ON = 1,
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RGX_RD_POWER_ISLAND_DEFAULT = 2
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} RGX_RD_POWER_ISLAND_CONF;
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typedef enum
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{
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RGX_META_T1_OFF = 0x0, /*!< No thread 1 running (unless 2nd thread is used for HWPerf) */
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RGX_META_T1_MAIN = 0x1, /*!< Run the main thread 0 code on thread 1 (and vice versa if 2nd thread is used for HWPerf) */
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RGX_META_T1_DUMMY = 0x2 /*!< Run dummy test code on thread 1 */
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} RGX_META_T1_CONF;
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/*!
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******************************************************************************
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* Querying DM state
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*****************************************************************************/
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typedef enum _RGXFWIF_DM_STATE_
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{
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RGXFWIF_DM_STATE_NORMAL = 0,
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RGXFWIF_DM_STATE_LOCKEDUP = 1
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} RGXFWIF_DM_STATE;
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typedef struct
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{
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IMG_UINT16 ui16RegNum; /*!< Register number */
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IMG_UINT16 ui16IndirectRegNum; /*!< Indirect register number (or 0 if not used) */
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IMG_UINT16 ui16IndirectStartVal; /*!< Start value for indirect register */
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IMG_UINT16 ui16IndirectEndVal; /*!< End value for indirect register */
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} RGXFW_REGISTER_LIST;
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#endif /* __RGX_FWIF_H__ */
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/******************************************************************************
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End of file (rgx_fwif.h)
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******************************************************************************/
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