/*************************************************************************/ /*!
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@File
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@Title arm specific OS functions
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description OS functions who's implementation are processor specific
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#include <linux/platform_device.h>
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#include <linux/version.h>
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#include <linux/cpumask.h>
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#include <linux/dma-mapping.h>
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#include <asm/cacheflush.h>
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#include "pvrsrv_error.h"
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#include "img_types.h"
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#include "osfunc.h"
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#include "pvr_debug.h"
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#if defined(CONFIG_OUTER_CACHE)
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/* If you encounter a 64-bit ARM system with an outer cache, you'll need
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* to add the necessary code to manage that cache. See osfunc_arm.c
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* for an example of how to do so.
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*/
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#error "CONFIG_OUTER_CACHE not supported on arm64."
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#endif
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static void per_cpu_cache_flush(void *arg)
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{
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0))
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static IMG_BOOL bLog = IMG_TRUE;
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/*
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NOTE: Regarding arm64 global flush support on >= Linux v4.2:
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- Global cache flush support is deprecated from v4.2 onwards
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- Cache maintenance is done using UM/KM VA maintenance _only_
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- If you find that more time is spent in VA cache maintenance
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- Implement arm64 assembly sequence for global flush here
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- asm volatile ();
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- If you do not want to implement the global cache assembly
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- Disable KM cache maintenance support in UM cache.c
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- Remove this PVR_LOG message
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*/
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if (bLog)
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{
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PVR_LOG(("Global d-cache flush assembly not implemented, using rangebased flush"));
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bLog = IMG_FALSE;
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}
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#else
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flush_cache_all();
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#endif
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PVR_UNREFERENCED_PARAMETER(arg);
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}
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PVRSRV_ERROR OSCPUOperation(PVRSRV_CACHE_OP uiCacheOp)
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{
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PVRSRV_ERROR eError = PVRSRV_OK;
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switch(uiCacheOp)
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{
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case PVRSRV_CACHE_OP_CLEAN:
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case PVRSRV_CACHE_OP_FLUSH:
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case PVRSRV_CACHE_OP_INVALIDATE:
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on_each_cpu(per_cpu_cache_flush, NULL, 1);
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0))
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eError = PVRSRV_ERROR_NOT_IMPLEMENTED;
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#endif
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break;
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case PVRSRV_CACHE_OP_NONE:
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break;
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default:
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PVR_DPF((PVR_DBG_ERROR,
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"%s: Global cache operation type %d is invalid",
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__FUNCTION__, uiCacheOp));
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//eError = PVRSRV_ERROR_INVALID_PARAMS;
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PVR_ASSERT(0);
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break;
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}
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return eError;
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}
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void OSFlushCPUCacheRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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const struct dma_map_ops *dma_ops = get_dma_ops(psDevNode->psDevConfig->pvOSDevice);
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PVR_UNREFERENCED_PARAMETER(pvVirtStart);
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PVR_UNREFERENCED_PARAMETER(pvVirtEnd);
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dma_ops->sync_single_for_device(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_TO_DEVICE);
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dma_ops->sync_single_for_cpu(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_FROM_DEVICE);
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}
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void OSCleanCPUCacheRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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const struct dma_map_ops *dma_ops = get_dma_ops(psDevNode->psDevConfig->pvOSDevice);
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PVR_UNREFERENCED_PARAMETER(pvVirtStart);
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PVR_UNREFERENCED_PARAMETER(pvVirtEnd);
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dma_ops->sync_single_for_device(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_TO_DEVICE);
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}
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void OSInvalidateCPUCacheRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
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void *pvVirtStart,
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void *pvVirtEnd,
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IMG_CPU_PHYADDR sCPUPhysStart,
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IMG_CPU_PHYADDR sCPUPhysEnd)
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{
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const struct dma_map_ops *dma_ops = get_dma_ops(psDevNode->psDevConfig->pvOSDevice);
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PVR_UNREFERENCED_PARAMETER(pvVirtStart);
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PVR_UNREFERENCED_PARAMETER(pvVirtEnd);
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dma_ops->sync_single_for_cpu(psDevNode->psDevConfig->pvOSDevice, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_FROM_DEVICE);
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}
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PVRSRV_CACHE_OP_ADDR_TYPE OSCPUCacheOpAddressType(PVRSRV_CACHE_OP uiCacheOp)
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{
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PVR_UNREFERENCED_PARAMETER(uiCacheOp);
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return PVRSRV_CACHE_OP_ADDR_TYPE_PHYSICAL;
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}
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void OSUserModeAccessToPerfCountersEn(void)
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{
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/* FIXME: implement similarly to __arm__ */
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}
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