/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* otpdefs.h SROM/OTP definitions.
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*
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* Copyright (C) 1999-2019, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id$
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*/
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#ifndef _OTPDEFS_H_
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#define _OTPDEFS_H_
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/* SFLASH */
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#define SFLASH_ADDRESS_OFFSET_4368 0x1C000000u
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#define SFLASH_SKU_OFFSET_4368 0xEu
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#define SFLASH_MACADDR_OFFSET_4368 0x4u
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/*
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* In sflash based chips, first word in sflash says the length.
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* So only default value is defined here. Actual length is read
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* from sflash in dhdpcie_srom_sflash_health_chk
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* 0x0521 * 2 .x2 since length says number of words.
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*/
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#define SFLASH_LEN_4368 0xA42u
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#define SROM_ADDRESS_OFFSET_4355 0x0800u
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#define SROM_ADDRESS_OFFSET_4364 0xA000u
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#define SROM_ADDRESS_OFFSET_4377 0x0800u
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#define SROM_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset))
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#define SROM_MACADDR_OFFSET_4355 0x84u
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#define SROM_MACADDR_OFFSET_4364 0x82u
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#define SROM_MACADDR_OFFSET_4377 0xE2u
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#define SROM_SKU_OFFSET_4355 0x8Au
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#define SROM_SKU_OFFSET_4364 0x8Cu
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#define SROM_SKU_OFFSET_4377 0xECu
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#define SROM_CAL_SIG1_OFFSET_4355 0xB8u
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#define SROM_CAL_SIG2_OFFSET_4355 0xBAu
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#define SROM_CAL_SIG1_OFFSET_4364 0xA0u
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#define SROM_CAL_SIG2_OFFSET_4364 0xA2u
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#define SROM_CAL_SIG1 0x4c42u
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#define SROM_CAL_SIG2 0x424fu
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#define SROM_LEN_4355 512u
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#define SROM_LEN_4364 2048u
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#define SROM_LEN_4377 2048u
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#define OTP_USER_AREA_OFFSET_4355 0xC0u
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#define OTP_USER_AREA_OFFSET_4364 0xC0u
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#define OTP_USER_AREA_OFFSET_4368 0x120u
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#define OTP_USER_AREA_OFFSET_4377 0x120u
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#define OTP_OFFSET_4368 0x5000u
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#define OTP_OFFSET_4377 0x11000u
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#define OTP_CTRL1_VAL 0xFA0000
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#define OTP_ADDRESS(sih, offset) (SI_ENUM_BASE(sih) + (offset))
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#define OTP_VERSION_TUPLE_ID 0x15
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#define OTP_VENDOR_TUPLE_ID 0x80
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#define OTP_CIS_REGION_END_TUPLE_ID 0XFF
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#define PCIE_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0x3000)
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#define SPROM_CTRL_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_CTRL)
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#define SPROM_CTRL_OPCODE_READ_MASK 0x9FFFFFFF
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#define SPROM_CTRL_START_BUSY_MASK 0x80000000
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#define SPROM_ADDR(sih) (SI_ENUM_BASE(sih) + CC_SROM_ADDRESS)
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#define SPROM_DATA(sih) (SI_ENUM_BASE(sih) + CC_SROM_DATA)
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#define OTP_CTRL1_REG_ADDR(sih) (SI_ENUM_BASE(sih) + 0xF4)
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#define PMU_MINRESMASK_REG_ADDR(sih) (SI_ENUM_BASE(sih) + MINRESMASKREG)
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#define CHIP_COMMON_STATUS_REG_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CHIPST)
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#define CHIP_COMMON_CLKDIV2_ADDR(sih) (SI_ENUM_BASE(sih) + CC_CLKDIV2)
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#define CC_CLKDIV2_SPROMDIV_MASK 0x7u
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#define CC_CLKDIV2_SPROMDIV_VAL 0X4u
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#define CC_CHIPSTATUS_STRAP_BTUART_MASK 0x40u
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#define PMU_OTP_PWR_ON_MASK 0xC47
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#define PMU_PWRUP_DELAY 500 /* in us */
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#define DONGLE_TREFUP_PROGRAM_DELAY 5000 /* 5ms in us */
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#define SPROM_BUSY_POLL_DELAY 5 /* 5us */
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typedef enum {
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BCM4355_IDX = 0,
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BCM4364_IDX,
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BCM4368_IDX,
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BCM4377_IDX,
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BCMMAX_IDX
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} chip_idx_t;
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typedef enum {
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BCM4368_BTOP_IDX,
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BCM4377_BTOP_IDX,
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BCMMAX_BTOP_IDX
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} chip_idx_btop_t;
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typedef enum {
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BCM4368_SFLASH_IDX,
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BCMMAX_SFLASH_IDX
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} chip_idx_sflash_t;
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extern uint32 otp_addr_offsets[];
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extern uint32 otp_usrarea_offsets[];
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extern uint32 sku_offsets[];
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extern uint32 srf_addr_offsets[];
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extern uint32 supported_chips[];
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char *dhd_get_plat_sku(void);
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#endif /* _OTPDEFS_H */
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