/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Misc utility routines for accessing lhl specific features
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* of the SiliconBackplane-based Broadcom chips.
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*
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* Copyright (C) 1999-2019, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: hndpmu.c 547757 2015-04-13 10:18:04Z $
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*/
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#include <hndpmu.h>
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#include <hndlhl.h>
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#include <sbchipc.h>
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#include <hndsoc.h>
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#include <bcmdevs.h>
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#include <osl.h>
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#include <sbgci.h>
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#include <siutils.h>
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#include <bcmutils.h>
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#ifdef BCMULP
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#include <ulp.h>
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#endif // endif
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#define SI_LHL_EXT_WAKE_REQ_MASK_MAGIC 0x7FBBF7FF /* magic number for LHL EXT */
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/* PmuRev1 has a 24-bit PMU RsrcReq timer. However it pushes all other bits
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* upward. To make the code to run for all revs we use a variable to tell how
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* many bits we need to shift.
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*/
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#define FLAGS_SHIFT 14
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#define LHL_ERROR(args) printf args
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void
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si_lhl_setup(si_t *sih, osl_t *osh)
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{
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if (CHIPID(sih->chip) == BCM43012_CHIP_ID) {
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/* Enable PMU sleep mode0 */
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LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_2);
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/* Modify as per the
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BCM43012/LHL#LHL-RecommendedsettingforvariousPMUSleepModes:
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*/
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LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL);
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LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL);
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LHL_REG(sih, lhl_top_pwrdn_ctl_adr, LHL_PWRDN_CTL_MASK, LHL_PWRDN_SLEEP_CNT);
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LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL);
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} else if (BCM4347_CHIP(sih->chip)) {
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if (LHL_IS_PSMODE_1(sih)) {
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LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_1);
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} else {
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LHL_REG(sih, lhl_top_pwrseq_ctl_adr, LHL_PWRSEQ_CTL, PMU_SLEEP_MODE_0);
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}
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LHL_REG(sih, lhl_top_pwrup_ctl_adr, LHL_PWRUP_CTL_MASK, LHL_PWRUP_CTL_4347);
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LHL_REG(sih, lhl_top_pwrup2_ctl_adr, LHL_PWRUP2_CTL_MASK, LHL_PWRUP2_CTL);
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LHL_REG(sih, lhl_top_pwrdn_ctl_adr,
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LHL_PWRDN_CTL_MASK, LHL_PWRDN_SLEEP_CNT);
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LHL_REG(sih, lhl_top_pwrdn2_ctl_adr, LHL_PWRDN2_CTL_MASK, LHL_PWRDN2_CTL);
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/*
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* Enable wakeup on GPIO1, PCIE clkreq and perst signal,
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* GPIO[0] is mapped to GPIO1
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* GPIO[1] is mapped to PCIE perst
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* GPIO[2] is mapped to PCIE clkreq
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*/
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/* GPIO1 */
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/* Clear any old interrupt status */
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LHL_REG(sih, gpio_int_st_port_adr[0],
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1 << PCIE_GPIO1_GPIO_PIN, 1 << PCIE_GPIO1_GPIO_PIN);
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/* active high level trigger */
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LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_GPIO1_GPIO_PIN], ~0,
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1 << GCI_GPIO_STS_WL_DIN_SELECT);
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LHL_REG(sih, gpio_int_en_port_adr[0],
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1 << PCIE_GPIO1_GPIO_PIN, 1 << PCIE_GPIO1_GPIO_PIN);
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LHL_REG(sih, gpio_int_st_port_adr[0],
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1 << PCIE_GPIO1_GPIO_PIN, 1 << PCIE_GPIO1_GPIO_PIN);
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#if !defined(_CFEZ_)
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si_gci_set_functionsel(sih, 1, CC4347_FNSEL_SAMEASPIN);
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#endif // endif
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/* PCIE perst */
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LHL_REG(sih, gpio_int_st_port_adr[0],
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1 << PCIE_PERST_GPIO_PIN, 1 << PCIE_PERST_GPIO_PIN);
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LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_PERST_GPIO_PIN], ~0,
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(1 << GCI_GPIO_STS_EDGE_TRIG_BIT |
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1 << GCI_GPIO_STS_WL_DIN_SELECT));
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LHL_REG(sih, gpio_int_en_port_adr[0],
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1 << PCIE_PERST_GPIO_PIN, 1 << PCIE_PERST_GPIO_PIN);
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LHL_REG(sih, gpio_int_st_port_adr[0],
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1 << PCIE_PERST_GPIO_PIN, 1 << PCIE_PERST_GPIO_PIN);
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/* PCIE clkreq */
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LHL_REG(sih, gpio_int_st_port_adr[0],
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1 << PCIE_CLKREQ_GPIO_PIN, 1 << PCIE_CLKREQ_GPIO_PIN);
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LHL_REG(sih, gpio_ctrl_iocfg_p_adr[PCIE_CLKREQ_GPIO_PIN], ~0,
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(1 << GCI_GPIO_STS_EDGE_TRIG_BIT |
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1 << GCI_GPIO_STS_NEG_EDGE_TRIG_BIT |
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1 << GCI_GPIO_STS_WL_DIN_SELECT));
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LHL_REG(sih, gpio_int_en_port_adr[0],
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1 << PCIE_CLKREQ_GPIO_PIN, 1 << PCIE_CLKREQ_GPIO_PIN);
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LHL_REG(sih, gpio_int_st_port_adr[0],
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1 << PCIE_CLKREQ_GPIO_PIN, 1 << PCIE_CLKREQ_GPIO_PIN);
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}
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}
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/* To skip this function, specify a invalid "lpo_select" value in nvram */
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int
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si_lhl_set_lpoclk(si_t *sih, osl_t *osh, uint32 lpo_force)
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{
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gciregs_t *gciregs;
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uint clk_det_cnt, status;
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int lhl_wlclk_sel;
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uint32 lpo = 0;
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int timeout = 0;
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gciregs = si_setcore(sih, GCI_CORE_ID, 0);
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ASSERT(gciregs != NULL);
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/* Apply nvram override to lpo */
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if ((lpo_force == LHL_LPO_AUTO) && ((lpo = (uint32)getintvar(NULL, "lpo_select")) == 0)) {
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lpo = LHL_OSC_32k_ENAB;
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} else {
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lpo = lpo_force;
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}
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/* Power up the desired LPO */
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switch (lpo) {
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case LHL_EXT_LPO_ENAB:
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LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, 0);
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lhl_wlclk_sel = LHL_EXT_SEL;
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break;
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case LHL_LPO1_ENAB:
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LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, 0);
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lhl_wlclk_sel = LHL_LPO1_SEL;
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break;
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case LHL_LPO2_ENAB:
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LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, 0);
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lhl_wlclk_sel = LHL_LPO2_SEL;
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break;
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case LHL_OSC_32k_ENAB:
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LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, 0);
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lhl_wlclk_sel = LHL_32k_SEL;
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break;
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default:
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goto done;
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}
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LHL_REG(sih, lhl_clk_det_ctl_adr,
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LHL_CLK_DET_CTL_AD_CNTR_CLK_SEL, lhl_wlclk_sel);
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/* Detect the desired LPO */
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LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN, 0);
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LHL_REG(sih, lhl_clk_det_ctl_adr,
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LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR, LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR);
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timeout = 0;
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clk_det_cnt =
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((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
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LHL_CLK_DET_CNT_SHIFT);
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while (clk_det_cnt != 0 && timeout <= LPO_SEL_TIMEOUT) {
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OSL_DELAY(10);
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clk_det_cnt =
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((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
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LHL_CLK_DET_CNT_SHIFT);
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timeout++;
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}
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if (clk_det_cnt != 0) {
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LHL_ERROR(("Clock not present as clear did not work timeout = %d\n", timeout));
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goto error;
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}
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LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_CLR, 0);
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LHL_REG(sih, lhl_clk_det_ctl_adr, LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN,
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LHL_CLK_DET_CTL_ADR_LHL_CNTR_EN);
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clk_det_cnt =
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((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
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LHL_CLK_DET_CNT_SHIFT);
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timeout = 0;
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while (clk_det_cnt <= CLK_DET_CNT_THRESH && timeout <= LPO_SEL_TIMEOUT) {
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OSL_DELAY(10);
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clk_det_cnt =
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((R_REG(osh, &gciregs->lhl_clk_det_ctl_adr) & LHL_CLK_DET_CNT) >>
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LHL_CLK_DET_CNT_SHIFT);
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timeout++;
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}
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if (timeout >= LPO_SEL_TIMEOUT) {
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LHL_ERROR(("LPO is not available timeout = %u\n, timeout", timeout));
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goto error;
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}
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/* Select the desired LPO */
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LHL_REG(sih, lhl_main_ctl_adr,
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LHL_MAIN_CTL_ADR_LHL_WLCLK_SEL, (lhl_wlclk_sel) << LPO_SEL_SHIFT);
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status = ((R_REG(osh, &gciregs->lhl_clk_status_adr) & LHL_MAIN_CTL_ADR_FINAL_CLK_SEL) ==
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(unsigned)(((1 << lhl_wlclk_sel) << LPO_FINAL_SEL_SHIFT))) ? 1 : 0;
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timeout = 0;
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while (!status && timeout <= LPO_SEL_TIMEOUT) {
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OSL_DELAY(10);
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status =
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((R_REG(osh, &gciregs->lhl_clk_status_adr) & LHL_MAIN_CTL_ADR_FINAL_CLK_SEL) ==
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(unsigned)(((1 << lhl_wlclk_sel) << LPO_FINAL_SEL_SHIFT))) ? 1 : 0;
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timeout++;
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}
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if (timeout >= LPO_SEL_TIMEOUT) {
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LHL_ERROR(("LPO is not available timeout = %u\n, timeout", timeout));
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goto error;
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}
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/* Power down the rest of the LPOs */
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if (lpo != LHL_EXT_LPO_ENAB) {
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LHL_REG(sih, lhl_main_ctl_adr, EXTLPO_BUF_PD, EXTLPO_BUF_PD);
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}
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if (lpo != LHL_LPO1_ENAB) {
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LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_EN, LPO1_PD_EN);
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LHL_REG(sih, lhl_main_ctl_adr, LPO1_PD_SEL, LPO1_PD_SEL_VAL);
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}
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if (lpo != LHL_LPO2_ENAB) {
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LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_EN, LPO2_PD_EN);
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LHL_REG(sih, lhl_main_ctl_adr, LPO2_PD_SEL, LPO2_PD_SEL_VAL);
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}
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if (lpo != LHL_OSC_32k_ENAB) {
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LHL_REG(sih, lhl_main_ctl_adr, OSC_32k_PD, OSC_32k_PD);
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}
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if (lpo != RADIO_LPO_ENAB) {
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si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_06, LPO_SEL, 0);
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}
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done:
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return BCME_OK;
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error:
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ROMMABLE_ASSERT(0);
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return BCME_ERROR;
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}
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void
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si_lhl_timer_config(si_t *sih, osl_t *osh, int timer_type)
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{
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uint origidx;
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pmuregs_t *pmu = NULL;
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/* Remember original core before switch to chipc/pmu */
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origidx = si_coreidx(sih);
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if (AOB_ENAB(sih)) {
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pmu = si_setcore(sih, PMU_CORE_ID, 0);
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} else {
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pmu = si_setcoreidx(sih, SI_CC_IDX);
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}
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ASSERT(pmu != NULL);
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switch (timer_type) {
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case LHL_MAC_TIMER:
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/* Enable MAC Timer interrupt */
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LHL_REG(sih, lhl_wl_mactim0_intrp_adr,
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(LHL_WL_MACTIM0_INTRP_EN | LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER),
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(LHL_WL_MACTIM0_INTRP_EN | LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER));
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/* Programs bits for MACPHY_CLK_AVAIL and all its dependent bits in
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* MacResourceReqMask0.
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*/
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PMU_REG(sih, mac_res_req_mask, ~0, si_pmu_rsrc_macphy_clk_deps(sih, osh, 0));
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/* One time init of mac_res_req_timer to enable interrupt and clock request */
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HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
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PMUREGADDR(sih, pmu, pmu, mac_res_req_timer),
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((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
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if (si_numd11coreunits(sih) > 1) {
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LHL_REG(sih, lhl_wl_mactim1_intrp_adr,
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(LHL_WL_MACTIM0_INTRP_EN | LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER),
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(LHL_WL_MACTIM0_INTRP_EN | LHL_WL_MACTIM0_INTRP_EDGE_TRIGGER));
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PMU_REG(sih, mac_res_req_mask1, ~0,
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si_pmu_rsrc_macphy_clk_deps(sih, osh, 1));
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HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
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PMUREGADDR(sih, pmu, pmu, mac_res_req_timer1),
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((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
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}
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break;
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case LHL_ARM_TIMER:
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/* Enable ARM Timer interrupt */
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LHL_REG(sih, lhl_wl_armtim0_intrp_adr,
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(LHL_WL_ARMTIM0_INTRP_EN | LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER),
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(LHL_WL_ARMTIM0_INTRP_EN | LHL_WL_ARMTIM0_INTRP_EDGE_TRIGGER));
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/* Programs bits for HT_AVAIL and all its dependent bits in ResourceReqMask0 */
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PMU_REG(sih, res_req_mask, ~0, si_pmu_rsrc_ht_avail_clk_deps(sih, osh));
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/* One time init of res_req_timer to enable interrupt and clock request
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* For low power request only ALP (HT_AVAIL is anyway requested by res_req_mask)
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*/
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HND_PMU_SYNC_WR(sih, pmu, pmu, osh,
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PMUREGADDR(sih, pmu, pmu, res_req_timer),
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((PRRT_ALP_REQ | PRRT_HQ_REQ | PRRT_INTEN) << FLAGS_SHIFT));
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break;
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}
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/* Return to original core */
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si_setcoreidx(sih, origidx);
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}
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void
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si_lhl_timer_enable(si_t *sih)
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{
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/* Enable clks for pmu int propagation */
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PMU_REG(sih, pmuintctrl0, PMU_INTC_ALP_REQ, PMU_INTC_ALP_REQ);
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PMU_REG(sih, pmuintmask0, RSRC_INTR_MASK_TIMER_INT_0, RSRC_INTR_MASK_TIMER_INT_0);
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LHL_REG(sih, lhl_main_ctl_adr, LHL_FAST_WRITE_EN, LHL_FAST_WRITE_EN);
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PMU_REG(sih, pmucontrol_ext, PCTL_EXT_USE_LHL_TIMER, PCTL_EXT_USE_LHL_TIMER);
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}
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void
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si_lhl_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period)
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{
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gciregs_t *gciregs;
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if (CHIPID(sih->chip) == BCM43012_CHIP_ID) {
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gciregs = si_setcore(sih, GCI_CORE_ID, 0);
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ASSERT(gciregs != NULL);
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W_REG(osh, &gciregs->lhl_wl_ilp_val_adr, ilp_period);
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}
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}
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#ifdef BCMULP
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void
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si_lhl_disable_sdio_wakeup(si_t *sih)
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{
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/* Disable the interrupt */
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LHL_REG(sih, gpio_int_en_port_adr[0], (1 << ULP_SDIO_CMD_PIN), 0);
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/* Clear the pending interrupt status */
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LHL_REG(sih, gpio_int_st_port_adr[0], (1 << ULP_SDIO_CMD_PIN), (1 << ULP_SDIO_CMD_PIN));
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}
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void
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si_lhl_enable_sdio_wakeup(si_t *sih, osl_t *osh)
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{
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gciregs_t *gciregs;
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pmuregs_t *pmu;
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gciregs = si_setcore(sih, GCI_CORE_ID, 0);
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ASSERT(gciregs != NULL);
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if (CHIPID(sih->chip) == BCM43012_CHIP_ID) {
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/* For SDIO_CMD configure P8 for wake on negedge
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* LHL 0 -> edge trigger intr mode,
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* 1 -> neg edge trigger intr mode ,
|
* 6 -> din from wl side enable
|
*/
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OR_REG(osh, &gciregs->gpio_ctrl_iocfg_p_adr[ULP_SDIO_CMD_PIN],
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(1 << GCI_GPIO_STS_EDGE_TRIG_BIT |
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1 << GCI_GPIO_STS_NEG_EDGE_TRIG_BIT |
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1 << GCI_GPIO_STS_WL_DIN_SELECT));
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/* Clear any old interrupt status */
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OR_REG(osh, &gciregs->gpio_int_st_port_adr[0], 1 << ULP_SDIO_CMD_PIN);
|
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/* LHL GPIO[8] intr en , GPIO[8] is mapped to SDIO_CMD */
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/* Enable P8 to generate interrupt */
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OR_REG(osh, &gciregs->gpio_int_en_port_adr[0], 1 << ULP_SDIO_CMD_PIN);
|
|
/* Clear LHL GPIO status to trigger GCI Interrupt */
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OR_REG(osh, &gciregs->gci_intstat, GCI_INTSTATUS_LHLWLWAKE);
|
/* Enable LHL GPIO Interrupt to trigger GCI Interrupt */
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OR_REG(osh, &gciregs->gci_intmask, GCI_INTMASK_LHLWLWAKE);
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OR_REG(osh, &gciregs->gci_wakemask, GCI_WAKEMASK_LHLWLWAKE);
|
/* Note ->Enable GCI interrupt to trigger Chipcommon interrupt
|
* Set EciGciIntEn in IntMask and will be done from FCBS saved tuple
|
*/
|
/* Enable LHL to trigger extWake upto HT_AVAIL */
|
/* LHL GPIO Interrupt is mapped to extWake[7] */
|
pmu = si_setcore(sih, PMU_CORE_ID, 0);
|
ASSERT(pmu != NULL);
|
/* Set bit 4 and 7 in ExtWakeMask */
|
W_REG(osh, &pmu->extwakemask[0], CI_ECI | CI_WECI);
|
/* Program bits for MACPHY_CLK_AVAIL rsrc in ExtWakeReqMaskN */
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W_REG(osh, &pmu->extwakereqmask[0], SI_LHL_EXT_WAKE_REQ_MASK_MAGIC);
|
/* Program 0 (no need to request explicitly for any backplane clk) */
|
W_REG(osh, &pmu->extwakectrl, 0x0);
|
/* Note: Configure MAC/Ucode to receive interrupt
|
* it will be done from saved tuple using FCBS code
|
*/
|
}
|
}
|
#endif /* BCMULP */
|
|
lhl_reg_set_t lv_sleep_mode_4369_lhl_reg_set[] =
|
{
|
/* set wl_sleep_en */
|
{LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 0), (1 << 0)},
|
|
/* set top_pwrsw_en, top_slb_en, top_iso_en */
|
{LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), BCM_MASK32(5, 3), (0x0 << 3)},
|
|
/* set VMUX_asr_sel_en */
|
{LHL_REG_OFF(lhl_top_pwrseq_ctl_adr), (1 << 8), (1 << 8)},
|
|
/* lhl_lp_main_ctl_adr, disable lp_mode_en, set CSR and ASR field enables for LV mode */
|
{LHL_REG_OFF(lhl_lp_main_ctl_adr), BCM_MASK32(21, 0), 0x3F89FF},
|
|
/* lhl_lp_main_ctl1_adr, set CSR field values - CSR_adj - 0.64V and trim_adj -5mV */
|
{LHL_REG_OFF(lhl_lp_main_ctl1_adr), BCM_MASK32(23, 0), 0x9E8F97},
|
|
/* lhl_lp_main_ctl2_adr, set ASR field values - ASR_adj - 0.76V and trim_adj +5mV */
|
{LHL_REG_OFF(lhl_lp_main_ctl2_adr), BCM_MASK32(13, 0), 0x07EE},
|
|
/* lhl_lp_dn_ctl_adr, set down count for CSR fields- adj, mode, overi_dis */
|
{LHL_REG_OFF(lhl_lp_dn_ctl_adr), ~0, ((LHL4369_CSR_OVERI_DIS_DWN_CNT << 16) |
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(LHL4369_CSR_MODE_DWN_CNT << 8) | (LHL4369_CSR_ADJ_DWN_CNT << 0))},
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/* lhl_lp_up_ctl_adr, set up count for CSR fields- adj, mode, overi_dis */
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{LHL_REG_OFF(lhl_lp_up_ctl_adr), ~0, ((LHL4369_CSR_OVERI_DIS_UP_CNT << 16) |
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(LHL4369_CSR_MODE_UP_CNT << 8) | (LHL4369_CSR_ADJ_UP_CNT << 0))},
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/* lhl_lp_dn_ctl1_adr, set down count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
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{LHL_REG_OFF(lhl_lp_dn_ctl1_adr), ~0, ((LHL4369_VDDC_SW_DIS_DWN_CNT << 24) |
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(LHL4369_ASR_ADJ_DWN_CNT << 16) | (LHL4369_HPBG_CHOP_DIS_DWN_CNT << 0))},
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/* lhl_lp_up_ctl1_adr, set up count for hpbg_chop_dis, ASR_adj, vddc_sw_dis */
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{LHL_REG_OFF(lhl_lp_up_ctl1_adr), ~0, ((LHL4369_VDDC_SW_DIS_UP_CNT << 24) |
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(LHL4369_ASR_ADJ_UP_CNT << 16) | (LHL4369_HPBG_CHOP_DIS_UP_CNT << 0))},
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/* lhl_lp_dn_ctl4_adr, set down count for ASR fields -
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* clk4m_dis, lppfm_mode, mode_sel, manual_mode
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*/
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{LHL_REG_OFF(lhl_lp_dn_ctl4_adr), ~0, ((LHL4369_ASR_MANUAL_MODE_DWN_CNT << 24) |
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(LHL4369_ASR_MODE_SEL_DWN_CNT << 16) | (LHL4369_ASR_LPPFM_MODE_DWN_CNT << 8) |
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(LHL4369_ASR_CLK4M_DIS_DWN_CNT << 0))},
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/* lhl_lp_up_ctl4_adr, set up count for ASR fields -
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* clk4m_dis, lppfm_mode, mode_sel, manual_mode
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*/
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{LHL_REG_OFF(lhl_lp_up_ctl4_adr), ~0, ((LHL4369_ASR_MANUAL_MODE_UP_CNT << 24) |
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(LHL4369_ASR_MODE_SEL_UP_CNT << 16)| (LHL4369_ASR_LPPFM_MODE_UP_CNT << 8) |
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(LHL4369_ASR_CLK4M_DIS_UP_CNT << 0))},
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/* lhl_lp_dn_ctl3_adr, set down count for hpbg_pu, srbg_ref, ASR_overi_dis,
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* CSR_pfm_pwr_slice_en
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*/
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{LHL_REG_OFF(lhl_lp_dn_ctl3_adr), ~0, ((LHL4369_PFM_PWR_SLICE_DWN_CNT << 24) |
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(LHL4369_ASR_OVERI_DIS_DWN_CNT << 16) | (LHL4369_SRBG_REF_SEL_DWN_CNT << 8) |
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(LHL4369_HPBG_PU_EN_DWN_CNT << 0))},
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/* lhl_lp_up_ctl3_adr, set up count for hpbg_pu, srbg_ref, ASR_overi_dis,
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* CSR_pfm_pwr_slice_en
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*/
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{LHL_REG_OFF(lhl_lp_up_ctl3_adr), ~0, ((LHL4369_PFM_PWR_SLICE_UP_CNT << 24) |
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(LHL4369_ASR_OVERI_DIS_UP_CNT << 16) | (LHL4369_SRBG_REF_SEL_UP_CNT << 8) |
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(LHL4369_HPBG_PU_EN_UP_CNT << 0))},
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/* lhl_lp_dn_ctl2_adr, set down count for CSR_trim_adj */
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{LHL_REG_OFF(lhl_lp_dn_ctl2_adr), ~0, (LHL4369_CSR_TRIM_ADJ_DWN_CNT << 16)},
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/* lhl_lp_up_ctl2_adr, set up count for CSR_trim_adj */
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{LHL_REG_OFF(lhl_lp_up_ctl2_adr), ~0, (LHL4369_CSR_TRIM_ADJ_UP_CNT << 16)},
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/* lhl_lp_dn_ctl5_adr, set down count for ASR_trim_adj */
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{LHL_REG_OFF(lhl_lp_dn_ctl5_adr), ~0, (LHL4369_ASR_TRIM_ADJ_DWN_CNT << 0)},
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/* lhl_lp_up_ctl5_adr, set down count for ASR_trim_adj */
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{LHL_REG_OFF(lhl_lp_up_ctl5_adr), ~0, (LHL4369_ASR_TRIM_ADJ_UP_CNT << 0)},
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/* Change the default down count values for the resources */
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/* lhl_top_pwrdn_ctl_adr, set down count for top_level_sleep, iso, slb and pwrsw */
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{LHL_REG_OFF(lhl_top_pwrdn_ctl_adr), ~0, ((LHL4369_PWRSW_EN_DWN_CNT << 24) |
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(LHL4369_SLB_EN_DWN_CNT << 16) | (LHL4369_ISO_EN_DWN_CNT << 8))},
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/* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
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{LHL_REG_OFF(lhl_top_pwrdn2_ctl_adr), ~0, (LHL4369_VMUX_ASR_SEL_DWN_CNT << 16)},
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/* Change the default up count values for the resources */
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/* lhl_top_pwrup_ctl_adr, set up count for top_level_sleep, iso, slb and pwrsw */
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{LHL_REG_OFF(lhl_top_pwrup_ctl_adr), ~0, ((LHL4369_PWRSW_EN_UP_CNT << 24) |
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(LHL4369_SLB_EN_UP_CNT << 16) | (LHL4369_ISO_EN_UP_CNT << 8))},
|
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/* lhl_top_pwrdn2_ctl_adr, set down count for VMUX_asr_sel */
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{LHL_REG_OFF(lhl_top_pwrup2_ctl_adr), ~0, ((LHL4369_VMUX_ASR_SEL_UP_CNT << 16))},
|
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/* Enable lhl interrupt */
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{LHL_REG_OFF(gci_intmask), (1 << 30), (1 << 30)},
|
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/* Enable LHL Wake up */
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{LHL_REG_OFF(gci_wakemask), (1 << 30), (1 << 30)},
|
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/* Making forceOTPpwrOn 0 */
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{LHL_REG_OFF(otpcontrol), (1 << 16), 0}
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};
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/* LV sleep mode summary:
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* LV mode is where both ABUCK and CBUCK are programmed to low voltages during
|
* sleep, and VMUX selects ABUCK as VDDOUT_AON. LPLDO needs to power off.
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* With ASR ON, LPLDO OFF
|
*/
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void
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si_set_lv_sleep_mode_lhl_config_4369(si_t *sih)
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{
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uint i;
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uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0);
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lhl_reg_set_t *regs = lv_sleep_mode_4369_lhl_reg_set;
|
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/* Enable LHL LV mode:
|
* lhl_top_pwrseq_ctl_adr, set wl_sleep_en, iso_en, slb_en, pwrsw_en,VMUX_asr_sel_en
|
*/
|
for (i = 0; i < ARRAYSIZE(lv_sleep_mode_4369_lhl_reg_set); i++) {
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si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val);
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}
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}
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