/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Linux DHD Bus Module for PCIE
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*
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* Copyright (C) 1999-2019, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: dhd_pcie.h 816392 2019-04-24 14:39:02Z $
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*/
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#ifndef dhd_pcie_h
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#define dhd_pcie_h
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#include <bcmpcie.h>
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#include <hnd_cons.h>
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/* defines */
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#define PCIE_SHARED_VERSION PCIE_SHARED_VERSION_7
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#define PCMSGBUF_HDRLEN 0
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#define DONGLE_REG_MAP_SIZE (32 * 1024)
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#define DONGLE_TCM_MAP_SIZE (4096 * 1024)
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#define DONGLE_MIN_MEMSIZE (128 *1024)
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#ifdef DHD_DEBUG
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#define DHD_PCIE_SUCCESS 0
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#define DHD_PCIE_FAILURE 1
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#endif /* DHD_DEBUG */
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#define REMAP_ENAB(bus) ((bus)->remap)
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#define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
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#define MAX_DHD_TX_FLOWS 320
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/* user defined data structures */
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/* Device console log buffer state */
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#define CONSOLE_LINE_MAX 192u
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#define CONSOLE_BUFFER_MAX (8 * 1024)
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#ifdef IDLE_TX_FLOW_MGMT
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#define IDLE_FLOW_LIST_TIMEOUT 5000
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#define IDLE_FLOW_RING_TIMEOUT 5000
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#endif /* IDLE_TX_FLOW_MGMT */
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/* HWA enabled and inited */
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#define HWA_ACTIVE(dhd) (((dhd)->hwa_enable) && ((dhd)->hwa_inited))
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/* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
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#define IDMA_ENAB(dhd) ((dhd)->idma_enable)
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#define IDMA_ACTIVE(dhd) (((dhd)->idma_enable) && ((dhd)->idma_inited))
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#define IDMA_CAPABLE(bus) (((bus)->sih->buscorerev == 19) || ((bus)->sih->buscorerev >= 23))
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/* IFRM (Implicit Flow Ring Manager enable and inited */
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#define IFRM_ENAB(dhd) ((dhd)->ifrm_enable)
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#define IFRM_ACTIVE(dhd) (((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
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/* DAR registers use for h2d doorbell */
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#define DAR_ENAB(dhd) ((dhd)->dar_enable)
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#define DAR_ACTIVE(dhd) (((dhd)->dar_enable) && ((dhd)->dar_inited))
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/* DAR WAR for revs < 64 */
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#define DAR_PWRREQ(bus) (((bus)->_dar_war) && DAR_ACTIVE((bus)->dhd))
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/* PCIE CTO Prevention and Recovery */
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#define PCIECTO_ENAB(bus) ((bus)->cto_enable)
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/* Implicit DMA index usage :
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* Index 0 for h2d write index transfer
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* Index 1 for d2h read index transfer
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*/
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#define IDMA_IDX0 0
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#define IDMA_IDX1 1
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#define IDMA_IDX2 2
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#define IDMA_IDX3 3
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#define DMA_TYPE_SHIFT 4
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#define DMA_TYPE_IDMA 1
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#define DHDPCIE_CONFIG_HDR_SIZE 16
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#define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
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#define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
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#define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
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#define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
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#define DHDPCIE_PM_D2_DELAY 200 /* 200us */
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typedef struct dhd_console {
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uint count; /* Poll interval msec counter */
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uint log_addr; /* Log struct address (fixed) */
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hnd_log_t log; /* Log struct (host copy) */
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uint bufsize; /* Size of log buffer */
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uint8 *buf; /* Log buffer (host copy) */
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uint last; /* Last buffer read index */
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} dhd_console_t;
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typedef struct ring_sh_info {
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uint32 ring_mem_addr;
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uint32 ring_state_w;
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uint32 ring_state_r;
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} ring_sh_info_t;
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#define DEVICE_WAKE_NONE 0
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#define DEVICE_WAKE_OOB 1
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#define DEVICE_WAKE_INB 2
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#define INBAND_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_INB)
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#define OOB_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_OOB)
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#define NO_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_NONE)
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#define PCIE_RELOAD_WAR_ENAB(buscorerev) \
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((buscorerev == 66) || (buscorerev == 67) || (buscorerev == 68) || (buscorerev == 70))
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/*
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* HW JIRA - CRWLPCIEGEN2-672
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* Producer Index Feature which is used by F1 gets reset on F0 FLR
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* fixed in REV68
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*/
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#define PCIE_ENUM_RESET_WAR_ENAB(buscorerev) \
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((buscorerev == 66) || (buscorerev == 67))
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struct dhd_bus;
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struct dhd_pcie_rev {
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uint8 fw_rev;
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void (*handle_mb_data)(struct dhd_bus *);
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};
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typedef struct dhdpcie_config_save
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{
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uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
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/* pmcsr save */
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uint32 pmcsr;
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/* express save */
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uint32 exp_dev_ctrl_stat;
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uint32 exp_link_ctrl_stat;
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uint32 exp_dev_ctrl_stat2;
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uint32 exp_link_ctrl_stat2;
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/* msi save */
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uint32 msi_cap;
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uint32 msi_addr0;
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uint32 msi_addr1;
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uint32 msi_data;
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/* l1pm save */
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uint32 l1pm0;
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uint32 l1pm1;
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/* ltr save */
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uint32 ltr;
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/* aer save */
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uint32 aer_caps_ctrl; /* 0x18 */
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uint32 aer_severity; /* 0x0C */
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uint32 aer_umask; /* 0x08 */
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uint32 aer_cmask; /* 0x14 */
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uint32 aer_root_cmd; /* 0x2c */
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/* BAR0 and BAR1 windows */
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uint32 bar0_win;
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uint32 bar1_win;
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} dhdpcie_config_save_t;
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/* The level of bus communication with the dongle */
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enum dhd_bus_low_power_state {
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DHD_BUS_NO_LOW_POWER_STATE, /* Not in low power state */
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DHD_BUS_D3_INFORM_SENT, /* D3 INFORM sent */
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DHD_BUS_D3_ACK_RECIEVED, /* D3 ACK recieved */
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};
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/** Instantiated once for each hardware (dongle) instance that this DHD manages */
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typedef struct dhd_bus {
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dhd_pub_t *dhd; /**< pointer to per hardware (dongle) unique instance */
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struct pci_dev *rc_dev; /* pci RC device handle */
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struct pci_dev *dev; /* pci device handle */
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dll_t flowring_active_list; /* constructed list of tx flowring queues */
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#ifdef IDLE_TX_FLOW_MGMT
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uint64 active_list_last_process_ts;
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/* stores the timestamp of active list processing */
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#endif /* IDLE_TX_FLOW_MGMT */
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si_t *sih; /* Handle for SI calls */
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char *vars; /* Variables (from CIS and/or other) */
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uint varsz; /* Size of variables buffer */
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uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
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sbpcieregs_t *reg; /* Registers for PCIE core */
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uint armrev; /* CPU core revision */
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uint coreid; /* CPU core id */
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uint ramrev; /* SOCRAM core revision */
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uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
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uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
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bool ramsize_adjusted; /* flag to note adjustment, so that
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* adjustment routine and file io
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* are avoided on D3 cold -> D0
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*/
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uint32 srmemsize; /* Size of SRMEM */
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uint32 bus; /* gSPI or SDIO bus */
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uint32 intstatus; /* Intstatus bits (events) pending */
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bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
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bool fcstate; /* State of dongle flow-control */
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uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
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char *fw_path; /* module_param: path to firmware image */
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char *nv_path; /* module_param: path to nvram vars file */
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struct pktq txq; /* Queue length used for flow-control */
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bool intr; /* Use interrupts */
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bool poll; /* Use polling */
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bool ipend; /* Device interrupt is pending */
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bool intdis; /* Interrupts disabled by isr */
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uint intrcount; /* Count of device interrupt callbacks */
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uint lastintrs; /* Count as of last watchdog timer */
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dhd_console_t console; /* Console output polling support */
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uint console_addr; /* Console address from shared struct */
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bool alp_only; /* Don't use HT clock (ALP only) */
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bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
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* Available with socram rev 16
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* Remap region not DMA-able
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*/
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uint32 resetinstr;
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uint32 dongle_ram_base;
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ulong shared_addr;
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pciedev_shared_t *pcie_sh;
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uint32 dma_rxoffset;
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volatile char *regs; /* pci device memory va */
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volatile char *tcm; /* pci device memory va */
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osl_t *osh;
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uint32 nvram_csm; /* Nvram checksum */
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uint16 pollrate;
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uint16 polltick;
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volatile uint32 *pcie_mb_intr_addr;
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volatile uint32 *pcie_mb_intr_2_addr;
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void *pcie_mb_intr_osh;
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bool sleep_allowed;
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wake_counts_t wake_counts;
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/* version 3 shared struct related info start */
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ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
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uint8 h2d_ring_count;
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uint8 d2h_ring_count;
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uint32 ringmem_ptr;
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uint32 ring_state_ptr;
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uint32 d2h_dma_scratch_buffer_mem_addr;
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uint32 h2d_mb_data_ptr_addr;
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uint32 d2h_mb_data_ptr_addr;
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/* version 3 shared struct related info end */
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uint32 def_intmask;
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uint32 d2h_mb_mask;
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uint32 pcie_mailbox_mask;
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uint32 pcie_mailbox_int;
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bool ltrsleep_on_unload;
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uint wait_for_d3_ack;
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uint16 max_tx_flowrings;
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uint16 max_submission_rings;
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uint16 max_completion_rings;
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uint16 max_cmn_rings;
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uint32 rw_index_sz;
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bool db1_for_mb;
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dhd_timeout_t doorbell_timer;
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bool device_wake_state;
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bool irq_registered;
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bool d2h_intr_method;
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int32 idletime; /* Control for activity timeout */
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uint32 d3_inform_cnt;
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uint32 d0_inform_cnt;
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uint32 d0_inform_in_use_cnt;
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uint8 force_suspend;
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uint8 is_linkdown;
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uint8 no_bus_init;
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#ifdef IDLE_TX_FLOW_MGMT
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bool enable_idle_flowring_mgmt;
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#endif /* IDLE_TX_FLOW_MGMT */
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struct dhd_pcie_rev api;
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bool use_mailbox;
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bool use_d0_inform;
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void *bus_lock;
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void *backplane_access_lock;
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enum dhd_bus_low_power_state bus_low_power_state;
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uint32 hostready_count; /* Number of hostready issued */
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#if defined(BCMPCIE_OOB_HOST_WAKE)
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bool oob_presuspend;
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#endif // endif
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dhdpcie_config_save_t saved_config;
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ulong resume_intr_enable_count;
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ulong dpc_intr_enable_count;
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ulong isr_intr_disable_count;
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ulong suspend_intr_disable_count;
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ulong dpc_return_busdown_count;
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ulong non_ours_irq_count;
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#ifdef BCMPCIE_OOB_HOST_WAKE
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ulong oob_intr_count;
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ulong oob_intr_enable_count;
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ulong oob_intr_disable_count;
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uint64 last_oob_irq_time;
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uint64 last_oob_irq_enable_time;
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uint64 last_oob_irq_disable_time;
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#endif /* BCMPCIE_OOB_HOST_WAKE */
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uint64 isr_entry_time;
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uint64 isr_exit_time;
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uint64 dpc_sched_time;
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uint64 dpc_entry_time;
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uint64 dpc_exit_time;
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uint64 resched_dpc_time;
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uint64 last_d3_inform_time;
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uint64 last_process_ctrlbuf_time;
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uint64 last_process_flowring_time;
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uint64 last_process_txcpl_time;
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uint64 last_process_rxcpl_time;
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uint64 last_process_infocpl_time;
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uint64 last_process_edl_time;
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uint64 last_suspend_start_time;
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uint64 last_suspend_end_time;
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uint64 last_resume_start_time;
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uint64 last_resume_end_time;
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uint64 last_non_ours_irq_time;
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uint8 hwa_enab_bmap;
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bool idma_enabled;
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bool ifrm_enabled;
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bool dar_enabled;
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uint32 dmaxfer_complete;
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uint8 dw_option;
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bool _dar_war;
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uint8 dma_chan;
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bool cto_enable; /* enable PCIE CTO Prevention and recovery */
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uint32 cto_threshold; /* PCIE CTO timeout threshold */
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bool cto_triggered; /* CTO is triggered */
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int pwr_req_ref;
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bool flr_force_fail; /* user intends to simulate flr force fail */
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bool intr_enabled; /* ready to receive interrupts from dongle */
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bool force_bt_quiesce; /* send bt_quiesce command to BT driver. */
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#if defined(DHD_H2D_LOG_TIME_SYNC)
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ulong dhd_rte_time_sync_count; /* OSL_SYSUPTIME_US() */
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#endif /* DHD_H2D_LOG_TIME_SYNC */
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bool rc_ep_aspm_cap; /* RC and EP ASPM capable */
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bool rc_ep_l1ss_cap; /* EC and EP L1SS capable */
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uint16 hp2p_txcpl_max_items;
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uint16 hp2p_rxcpl_max_items;
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/* PCIE coherent status */
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uint32 coherent_state;
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} dhd_bus_t;
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#ifdef DHD_MSI_SUPPORT
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extern uint enable_msi;
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#endif /* DHD_MSI_SUPPORT */
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enum {
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PCIE_INTX = 0,
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PCIE_MSI = 1
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};
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/* function declarations */
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extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
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extern int dhdpcie_bus_register(void);
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extern void dhdpcie_bus_unregister(void);
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extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
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extern int dhdpcie_bus_attach(osl_t *osh, dhd_bus_t **bus_ptr,
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volatile char *regs, volatile char *tcm, void *pci_dev);
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extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
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extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
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extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
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extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
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extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
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extern void dhdpcie_bus_release(struct dhd_bus *bus);
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extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
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extern void dhdpcie_free_irq(dhd_bus_t *bus);
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extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
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extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value, bool devwake);
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extern void dhdpcie_dongle_reset(dhd_bus_t *bus);
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#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
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extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state, bool byint);
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#else
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extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
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#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
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extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
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extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
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extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus, int force_l1_entry_time);
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extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
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extern void dhdpcie_pme_active(osl_t *osh, bool enable);
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extern bool dhdpcie_pme_cap(osl_t *osh);
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extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
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extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus, uint min_res_mask);
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extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
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extern int dhdpcie_disable_irq(dhd_bus_t *bus);
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extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
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extern int dhdpcie_enable_irq(dhd_bus_t *bus);
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extern void dhd_bus_dump_dar_registers(struct dhd_bus *bus);
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extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
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extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
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bool is_write, uint32 writeval);
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extern uint32 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext,
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bool is_write, uint32 writeval);
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extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
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extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
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extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
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extern int dhdpcie_disable_device(dhd_bus_t *bus);
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extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
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extern void dhdpcie_free_resource(dhd_bus_t *bus);
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extern void dhdpcie_dump_resource(dhd_bus_t *bus);
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extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
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void dhdpcie_os_setbar1win(dhd_bus_t *bus, uint32 addr);
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void dhdpcie_os_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
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uint8 dhdpcie_os_rtcm8(dhd_bus_t *bus, ulong offset);
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void dhdpcie_os_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
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uint16 dhdpcie_os_rtcm16(dhd_bus_t *bus, ulong offset);
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void dhdpcie_os_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
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uint32 dhdpcie_os_rtcm32(dhd_bus_t *bus, ulong offset);
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#ifdef DHD_SUPPORT_64BIT
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void dhdpcie_os_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
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uint64 dhdpcie_os_rtcm64(dhd_bus_t *bus, ulong offset);
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#endif // endif
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extern int dhdpcie_enable_device(dhd_bus_t *bus);
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#ifdef BCMPCIE_OOB_HOST_WAKE
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extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
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extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
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extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
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extern int dhdpcie_get_oob_irq_num(struct dhd_bus *bus);
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extern int dhdpcie_get_oob_irq_status(struct dhd_bus *bus);
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extern int dhdpcie_get_oob_irq_level(void);
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#endif /* BCMPCIE_OOB_HOST_WAKE */
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#if defined(CONFIG_ARCH_EXYNOS)
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#define SAMSUNG_PCIE_VENDOR_ID 0x144d
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#if defined(CONFIG_MACH_UNIVERSAL7420) || defined(CONFIG_SOC_EXYNOS7420)
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#define SAMSUNG_PCIE_DEVICE_ID 0xa575
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#define SAMSUNG_PCIE_CH_NUM 1
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#elif defined(CONFIG_SOC_EXYNOS8890)
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#define SAMSUNG_PCIE_DEVICE_ID 0xa544
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#define SAMSUNG_PCIE_CH_NUM 0
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#elif defined(CONFIG_SOC_EXYNOS8895) || defined(CONFIG_SOC_EXYNOS9810) || \
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defined(CONFIG_SOC_EXYNOS9820)
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#define SAMSUNG_PCIE_DEVICE_ID 0xecec
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#define SAMSUNG_PCIE_CH_NUM 0
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#else
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#error "Not supported platform"
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#endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
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#endif /* CONFIG_ARCH_EXYNOS */
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#if defined(CONFIG_ARCH_MSM)
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#define MSM_PCIE_VENDOR_ID 0x17cb
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#if defined(CONFIG_ARCH_APQ8084)
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#define MSM_PCIE_DEVICE_ID 0x0101
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#elif defined(CONFIG_ARCH_MSM8994)
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#define MSM_PCIE_DEVICE_ID 0x0300
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#elif defined(CONFIG_ARCH_MSM8996)
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#define MSM_PCIE_DEVICE_ID 0x0104
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#elif defined(CONFIG_ARCH_MSM8998)
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#define MSM_PCIE_DEVICE_ID 0x0105
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#elif defined(CONFIG_ARCH_SDM845) || defined(CONFIG_ARCH_SM8150)
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#define MSM_PCIE_DEVICE_ID 0x0106
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#else
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#error "Not supported platform"
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#endif // endif
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#endif /* CONFIG_ARCH_MSM */
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#if defined(CONFIG_X86)
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#define X86_PCIE_VENDOR_ID 0x8086
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#define X86_PCIE_DEVICE_ID 0x9c1a
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#endif /* CONFIG_X86 */
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#if defined(CONFIG_ARCH_TEGRA)
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#define TEGRA_PCIE_VENDOR_ID 0x14e4
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#define TEGRA_PCIE_DEVICE_ID 0x4347
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#endif /* CONFIG_ARCH_TEGRA */
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#define HIKEY_PCIE_VENDOR_ID 0x19e5
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#define HIKEY_PCIE_DEVICE_ID 0x3660
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#define DUMMY_PCIE_VENDOR_ID 0xffff
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#define DUMMY_PCIE_DEVICE_ID 0xffff
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#if defined(CONFIG_ARCH_EXYNOS)
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#define PCIE_RC_VENDOR_ID SAMSUNG_PCIE_VENDOR_ID
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#define PCIE_RC_DEVICE_ID SAMSUNG_PCIE_DEVICE_ID
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#elif defined(CONFIG_ARCH_MSM)
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#define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
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#define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
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#elif defined(CONFIG_X86)
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#define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
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#define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
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#elif defined(CONFIG_ARCH_TEGRA)
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#define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
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#define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
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#else
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#define PCIE_RC_VENDOR_ID HIKEY_PCIE_VENDOR_ID
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#define PCIE_RC_DEVICE_ID HIKEY_PCIE_DEVICE_ID
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#endif /* CONFIG_ARCH_EXYNOS */
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#define DHD_REGULAR_RING 0
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#define DHD_HP2P_RING 1
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#ifdef USE_EXYNOS_PCIE_RC_PMPATCH
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extern int exynos_pcie_pm_suspend(int ch_num);
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extern int exynos_pcie_pm_resume(int ch_num);
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#endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
|
|
#ifdef CONFIG_ARCH_TEGRA
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extern int tegra_pcie_pm_suspend(void);
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extern int tegra_pcie_pm_resume(void);
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#endif /* CONFIG_ARCH_TEGRA */
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|
extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
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#ifdef IDLE_TX_FLOW_MGMT
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extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
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extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
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extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
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extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus, uint16 flowid, uint32 status);
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extern void dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
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flow_ring_node_t *flow_ring_node);
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extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
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flow_ring_node_t *flow_ring_node);
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extern void dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
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flow_ring_node_t *flow_ring_node);
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extern void __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
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flow_ring_node_t *flow_ring_node);
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#endif /* IDLE_TX_FLOW_MGMT */
|
|
extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
|
|
#ifdef DHD_WAKE_STATUS
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int bcmpcie_get_total_wake(struct dhd_bus *bus);
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int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
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#endif /* DHD_WAKE_STATUS */
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extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
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extern void dhd_bus_hostready(struct dhd_bus *bus);
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extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
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extern int dhdpcie_irq_disabled(struct dhd_bus *bus);
|
|
static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus) {return TRUE;}
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static INLINE int dhd_os_wifi_platform_set_power(uint32 value) {return BCME_OK; }
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static INLINE void
|
dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t *bus)
|
{ return; }
|
|
int dhdpcie_config_check(dhd_bus_t *bus);
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int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
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int dhdpcie_config_save(dhd_bus_t *bus);
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int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
|
|
extern bool dhdpcie_bus_get_pcie_hwa_supported(dhd_bus_t *bus);
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extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
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extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
|
extern bool dhdpcie_bus_get_pcie_dar_supported(dhd_bus_t *bus);
|
|
static INLINE uint32
|
dhd_pcie_config_read(osl_t *osh, uint offset, uint size)
|
{
|
OSL_DELAY(100);
|
return OSL_PCI_READ_CONFIG(osh, offset, size);
|
}
|
|
static INLINE uint32
|
dhd_pcie_corereg_read(si_t *sih, uint val)
|
{
|
OSL_DELAY(100);
|
si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, val);
|
return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), 0, 0);
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}
|
|
extern int dhdpcie_get_fwpath_otp(dhd_bus_t *bus, char *fw_path, char *nv_path,
|
char *clm_path, char *txcap_path);
|
|
extern int dhd_pcie_debug_info_dump(dhd_pub_t *dhd);
|
extern void dhd_pcie_intr_count_dump(dhd_pub_t *dhd);
|
extern void dhdpcie_bus_clear_intstatus(dhd_bus_t *bus);
|
#ifdef DHD_HP2P
|
extern uint16 dhd_bus_get_hp2p_ring_max_size(dhd_bus_t *bus, bool tx);
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#endif // endif
|
|
#endif /* dhd_pcie_h */
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