/*
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* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
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* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef RXE_OPCODE_H
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#define RXE_OPCODE_H
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/*
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* contains header bit mask definitions and header lengths
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* declaration of the rxe_opcode_info struct and
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* rxe_wr_opcode_info struct
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*/
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enum rxe_wr_mask {
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WR_INLINE_MASK = BIT(0),
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WR_ATOMIC_MASK = BIT(1),
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WR_SEND_MASK = BIT(2),
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WR_READ_MASK = BIT(3),
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WR_WRITE_MASK = BIT(4),
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WR_LOCAL_MASK = BIT(5),
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WR_REG_MASK = BIT(6),
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WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK,
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WR_READ_WRITE_OR_SEND_MASK = WR_READ_OR_WRITE_MASK | WR_SEND_MASK,
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WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK,
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WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK,
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};
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#define WR_MAX_QPT (8)
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struct rxe_wr_opcode_info {
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char *name;
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enum rxe_wr_mask mask[WR_MAX_QPT];
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};
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extern struct rxe_wr_opcode_info rxe_wr_opcode_info[];
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enum rxe_hdr_type {
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RXE_LRH,
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RXE_GRH,
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RXE_BTH,
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RXE_RETH,
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RXE_AETH,
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RXE_ATMETH,
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RXE_ATMACK,
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RXE_IETH,
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RXE_RDETH,
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RXE_DETH,
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RXE_IMMDT,
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RXE_PAYLOAD,
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NUM_HDR_TYPES
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};
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enum rxe_hdr_mask {
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RXE_LRH_MASK = BIT(RXE_LRH),
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RXE_GRH_MASK = BIT(RXE_GRH),
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RXE_BTH_MASK = BIT(RXE_BTH),
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RXE_IMMDT_MASK = BIT(RXE_IMMDT),
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RXE_RETH_MASK = BIT(RXE_RETH),
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RXE_AETH_MASK = BIT(RXE_AETH),
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RXE_ATMETH_MASK = BIT(RXE_ATMETH),
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RXE_ATMACK_MASK = BIT(RXE_ATMACK),
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RXE_IETH_MASK = BIT(RXE_IETH),
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RXE_RDETH_MASK = BIT(RXE_RDETH),
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RXE_DETH_MASK = BIT(RXE_DETH),
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RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD),
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RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0),
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RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1),
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RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2),
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RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3),
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RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4),
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RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5),
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RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6),
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RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7),
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RXE_START_MASK = BIT(NUM_HDR_TYPES + 8),
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RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9),
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RXE_END_MASK = BIT(NUM_HDR_TYPES + 10),
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RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12),
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RXE_READ_OR_ATOMIC = (RXE_READ_MASK | RXE_ATOMIC_MASK),
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RXE_WRITE_OR_SEND = (RXE_WRITE_MASK | RXE_SEND_MASK),
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};
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#define OPCODE_NONE (-1)
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#define RXE_NUM_OPCODE 256
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struct rxe_opcode_info {
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char *name;
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enum rxe_hdr_mask mask;
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int length;
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int offset[NUM_HDR_TYPES];
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};
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extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE];
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#endif /* RXE_OPCODE_H */
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