/*
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* arch/arm/mach-ks8695/include/mach/regs-irq.h
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*
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* Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
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* Copyright (C) 2006 Simtec Electronics
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*
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* KS8695 - IRQ registers and bit definitions
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_IRQ_H
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#define KS8695_IRQ_H
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#define KS8695_IRQ_OFFSET (0xF0000 + 0xE200)
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#define KS8695_IRQ_VA (KS8695_IO_VA + KS8695_IRQ_OFFSET)
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#define KS8695_IRQ_PA (KS8695_IO_PA + KS8695_IRQ_OFFSET)
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/*
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* Interrupt Controller registers
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*/
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#define KS8695_INTMC (0x00) /* Mode Control Register */
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#define KS8695_INTEN (0x04) /* Interrupt Enable Register */
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#define KS8695_INTST (0x08) /* Interrupt Status Register */
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#define KS8695_INTPW (0x0c) /* Interrupt Priority (WAN MAC) */
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#define KS8695_INTPH (0x10) /* Interrupt Priority (HPNA) [KS8695 only] */
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#define KS8695_INTPL (0x14) /* Interrupt Priority (LAN MAC) */
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#define KS8695_INTPT (0x18) /* Interrupt Priority (Timer) */
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#define KS8695_INTPU (0x1c) /* Interrupt Priority (UART) */
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#define KS8695_INTPE (0x20) /* Interrupt Priority (External Interrupt) */
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#define KS8695_INTPC (0x24) /* Interrupt Priority (Communications Channel) */
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#define KS8695_INTPBE (0x28) /* Interrupt Priority (Bus Error Response) */
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#define KS8695_INTMS (0x2c) /* Interrupt Mask Status Register */
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#define KS8695_INTHPF (0x30) /* Interrupt Pending Highest Priority (FIQ) */
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#define KS8695_INTHPI (0x34) /* Interrupt Pending Highest Priority (IRQ) */
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#endif
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