/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_VDPU34X_VP9D_H__
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#define __HAL_VDPU34X_VP9D_H__
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#include "rk_type.h"
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#include "vdpu34x_com.h"
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typedef struct Vdpu34xRegVp9dParam_t {
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struct SWREG64_VP9_SET {
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RK_U32 cprheader_offset : 16;
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RK_U32 reserve : 16;
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} reg64;
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struct SWREG65_CUR_POC {
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RK_U32 cur_poc : 32;
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} reg65;
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RK_U32 reg66;
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struct SWREG67_74_VP9_SEGID_GRP {
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RK_U32 segid_abs_delta : 1;
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RK_U32 segid_frame_qp_delta_en : 1;
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RK_U32 segid_frame_qp_delta : 9;
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RK_U32 segid_frame_loopfitler_value_en : 1;
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RK_U32 segid_frame_loopfilter_value : 7;
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RK_U32 segid_referinfo_en : 1;
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RK_U32 segid_referinfo : 2;
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RK_U32 segid_frame_skip_en : 1;
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RK_U32 reserve : 9;
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} reg67_74[8];
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struct SWREG75_VP9_INFO_LASTFRAME {
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RK_U32 mode_deltas_lastframe : 14;
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RK_U32 vp9_segment_id_clear : 1;
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RK_U32 vp9_segment_id_update : 1;
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RK_U32 segmentation_enable_lstframe : 1;
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RK_U32 last_show_frame : 1;
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RK_U32 last_intra_only : 1;
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RK_U32 last_widthheight_eqcur : 1;
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RK_U32 color_space_lastkeyframe : 3;
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RK_U32 reserve1 : 9;
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} reg75;
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struct SWREG76_VP9_CPRHEADER_CONFIG {
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RK_U32 tx_mode : 3;
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RK_U32 frame_reference_mode : 2;
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RK_U32 reserve : 27;
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} reg76;
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struct SWREG77_VP9_INTERCMD_NUM {
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RK_U32 intercmd_num : 24;
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RK_U32 reserve : 8;
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} reg77;
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struct SWREG78_VP9_LASTTILE_SIZE {
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RK_U32 lasttile_size : 24;
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RK_U32 reserve : 8;
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} reg78;
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struct SWREG79_VP9_LASTF_Y_HOR_VIRSTRIDE {
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RK_U32 lastfy_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg79;
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struct SWREG80_VP9_LASTF_UV_HOR_VIRSTRIDE {
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RK_U32 lastfuv_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg80;
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struct SWREG81_VP9_GOLDENF_Y_HOR_VIRSTRIDE {
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RK_U32 goldenfy_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg81;
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struct SWREG82_VP9_GOLDENF_UV_HOR_VIRSTRIDE {
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RK_U32 goldenfuv_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg82;
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struct SWREG83_VP9_ALTREFF_Y_HOR_VIRSTRIDE {
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RK_U32 altreffy_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg83;
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struct SWREG84_VP9_ALTREFF_UV_HOR_VIRSTRIDE {
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RK_U32 altreffuv_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg84;
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struct SWREG85_VP9_LASTF_Y_VIRSTRIDE {
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RK_U32 lastfy_virstride : 28;
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RK_U32 reserve : 4;
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} reg85;
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struct SWREG86_VP9_GOLDEN_Y_VIRSTRIDE {
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RK_U32 goldeny_virstride : 28;
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RK_U32 reserve : 4;
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} reg86;
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struct SWREG87_VP9_ALTREF_Y_VIRSTRIDE {
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RK_U32 altrefy_virstride : 28;
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RK_U32 reserve : 4;
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} reg87;
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struct SWREG88_VP9_LREF_HOR_SCALE {
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RK_U32 lref_hor_scale : 16;
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RK_U32 reserve : 16;
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} reg88;
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struct SWREG89_VP9_LREF_VER_SCALE {
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RK_U32 lref_ver_scale : 16;
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RK_U32 reserve : 16;
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} reg89;
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struct SWREG90_VP9_GREF_HOR_SCALE {
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RK_U32 gref_hor_scale : 16;
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RK_U32 reserve : 16;
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} reg90;
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struct SWREG91_VP9_GREF_VER_SCALE {
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RK_U32 gref_ver_scale : 16;
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RK_U32 reserve : 16;
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} reg91;
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struct SWREG92_VP9_AREF_HOR_SCALE {
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RK_U32 aref_hor_scale : 16;
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RK_U32 reserve : 16;
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} reg92;
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struct SWREG93_VP9_AREF_VER_SCALE {
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RK_U32 aref_ver_scale : 16;
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RK_U32 reserve : 16;
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} reg93;
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struct SWREG94_VP9_REF_DELTAS_LASTFRAME {
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RK_U32 ref_deltas_lastframe : 28;
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RK_U32 reserve : 4;
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} reg94;
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struct SWREG95_LAST_POC {
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RK_U32 last_poc : 32;
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} reg95;
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struct SWREG96_GOLDEN_POC {
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RK_U32 golden_poc : 32;
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} reg96;
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struct SWREG97_ALTREF_POC {
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RK_U32 altref_poc : 32;
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} reg97;
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struct SWREG98_COF_REF_POC {
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RK_U32 col_ref_poc : 32;
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} reg98;
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struct SWREG99_PROB_REF_POC {
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RK_U32 prob_ref_poc : 32;
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} reg99;
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struct SWREG100_SEGID_REF_POC {
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RK_U32 segid_ref_poc : 32;
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} reg100;
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RK_U32 reg101_102_no_use[2];
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struct SWREG103_VP9_PROB_EN {
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RK_U32 reserve : 20;
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RK_U32 prob_update_en : 1;
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RK_U32 refresh_en : 1;
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RK_U32 prob_save_en : 1;
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RK_U32 intra_only_flag : 1;
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RK_U32 txfmmode_rfsh_en : 1;
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RK_U32 ref_mode_rfsh_en : 1;
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RK_U32 single_ref_rfsh_en : 1;
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RK_U32 comp_ref_rfsh_en : 1;
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RK_U32 interp_filter_switch_en : 1;
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RK_U32 allow_high_precision_mv : 1;
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RK_U32 last_key_frame_flag : 1;
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RK_U32 inter_coef_rfsh_flag : 1;
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} reg103;
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RK_U32 reg104_no_use;
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struct SWREG105_VP9CNT_UPD_EN_AVS2_HEADLEN {
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RK_U32 avs2_head_len : 4;
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RK_U32 count_update_en : 1;
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RK_U32 reserve : 27;
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} reg105;
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struct SWREG106_VP9_FRAME_WIDTH_LAST {
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RK_U32 framewidth_last : 16;
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RK_U32 reserve : 16;
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} reg106;
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struct SWREG107_VP9_FRAME_HEIGHT_LAST {
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RK_U32 frameheight_last : 16;
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RK_U32 reserve : 16;
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} reg107;
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struct SWREG108_VP9_FRAME_WIDTH_GOLDEN {
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RK_U32 framewidth_golden : 16;
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RK_U32 reserve : 16;
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} reg108;
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struct SWREG109_VP9_FRAME_HEIGHT_GOLDEN {
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RK_U32 frameheight_golden : 16;
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RK_U32 reserve : 16;
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} reg109;
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struct SWREG110_VP9_FRAME_WIDTH_ALTREF {
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RK_U32 framewidth_alfter : 16;
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RK_U32 reserve : 16;
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} reg110;
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struct SWREG111_VP9_FRAME_HEIGHT_ALTREF {
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RK_U32 frameheight_alfter : 16;
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RK_U32 reserve : 16;
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} reg111;
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struct SWREG112_ERROR_REF_INFO {
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RK_U32 ref_error_field : 1;
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RK_U32 ref_error_topfield : 1;
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RK_U32 ref_error_topfield_used : 1;
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RK_U32 ref_error_botfield_used : 1;
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RK_U32 reserve : 28;
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} reg112;
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} Vdpu34xRegVp9dParam;
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typedef struct Vdpu34xRegVp9dAddr_t {
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RK_U32 reg160_delta_prob_base;
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RK_U32 reg161_pps_base;
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RK_U32 reg162_last_prob_base;
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RK_U32 reg163_rps_base;
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RK_U32 reg164_ref_last_base;
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RK_U32 reg165_ref_golden_base;
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RK_U32 reg166_ref_alfter_base;
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RK_U32 reg167_count_prob_base;
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RK_U32 reg168_segidlast_base;
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RK_U32 reg169_segidcur_base;
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RK_U32 reg170_ref_colmv_base;
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RK_U32 reg171_intercmd_base;
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RK_U32 reg172_update_prob_wr_base;
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RK_U32 reg173_179_no_use[7];
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RK_U32 reg180_scanlist_base;
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RK_U32 reg181_196_ref_colmv_base[16];
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RK_U32 reg197_cabactbl_base;
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} Vdpu34xRegVp9dAddr;
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typedef struct Vdpu34xVp9dRegSet_t {
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Vdpu34xRegCommon common;
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Vdpu34xRegVp9dParam vp9d_param;
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Vdpu34xRegCommonAddr common_addr;
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Vdpu34xRegVp9dAddr vp9d_addr;
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Vdpu34xRegIrqStatus irq_status;
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Vdpu34xRegStatistic statistic;
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} Vdpu34xVp9dRegSet;
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#endif /* __HAL_VDPU34X_VP9D_H__ */
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