/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __VDPU34X_H265D_H__
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#define __VDPU34X_H265D_H__
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#include "vdpu34x_com.h"
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typedef struct Vdpu34xRegH265d_t {
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struct SWREG64_H26X_SET {
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RK_U32 h26x_frame_orslice : 1;
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RK_U32 h26x_rps_mode : 1;
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RK_U32 h26x_stream_mode : 1;
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RK_U32 h26x_stream_lastpacket : 1;
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RK_U32 h264_firstslice_flag : 1;
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RK_U32 reserve : 27;
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} reg64;
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struct SWREG65_CUR_POC {
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RK_U32 cur_top_poc : 32;
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} reg65;
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struct SWREG66_H264_CUR_POC1 {
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RK_U32 cur_bot_poc : 32;
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} reg66;
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RK_U32 reg67_82_ref_poc[16];
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struct SWREG83_98_H264_REF_POC {
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RK_U32 ref_poc : 32;
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} ref_poc_no_use[16];
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/* struct SWREG99_HEVC_REF_VALID{
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RK_U32 hevc_ref_valid : 15;
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RK_U32 reserve : 17;
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}hevc_ref_valid; */
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struct SWREG99_HEVC_REF_VALID {
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RK_U32 hevc_ref_valid_0 : 1;
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RK_U32 hevc_ref_valid_1 : 1;
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RK_U32 hevc_ref_valid_2 : 1;
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RK_U32 hevc_ref_valid_3 : 1;
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RK_U32 reserve0 : 4;
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RK_U32 hevc_ref_valid_4 : 1;
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RK_U32 hevc_ref_valid_5 : 1;
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RK_U32 hevc_ref_valid_6 : 1;
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RK_U32 hevc_ref_valid_7 : 1;
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RK_U32 reserve1 : 4;
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RK_U32 hevc_ref_valid_8 : 1;
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RK_U32 hevc_ref_valid_9 : 1;
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RK_U32 hevc_ref_valid_10 : 1;
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RK_U32 hevc_ref_valid_11 : 1;
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RK_U32 reserve2 : 4;
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RK_U32 hevc_ref_valid_12 : 1;
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RK_U32 hevc_ref_valid_13 : 1;
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RK_U32 hevc_ref_valid_14 : 1;
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RK_U32 reserve3 : 5;
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} reg99;
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RK_U32 reg100_102_no_use[3];
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struct SWREG103_HEVC_MVC0 {
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RK_U32 ref_pic_layer_same_with_cur : 16;
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RK_U32 reserve : 16;
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} reg103;
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struct SWREG104_HEVC_MVC1 {
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RK_U32 poc_lsb_not_present_flag : 1;
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RK_U32 num_direct_ref_layers : 6;
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RK_U32 reserve0 : 1;
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RK_U32 num_reflayer_pics : 6;
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RK_U32 default_ref_layers_active_flag : 1;
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RK_U32 max_one_active_ref_layer_flag : 1;
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RK_U32 poc_reset_info_present_flag : 1;
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RK_U32 vps_poc_lsb_aligned_flag : 1;
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RK_U32 mvc_poc15_valid_flag : 1;
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RK_U32 reserve1 : 13;
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} reg104;
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struct SWREG105_111_NO_USE_REGS {
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RK_U32 no_use_regs[7];
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} no_use_regs;
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struct SWREG112_ERROR_REF_INFO {
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RK_U32 avs2_ref_error_field : 1;
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RK_U32 avs2_ref_error_topfield : 1;
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RK_U32 ref_error_topfield_used : 1;
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RK_U32 ref_error_botfield_used : 1;
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RK_U32 reserve : 28;
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} reg112;
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} Vdpu34xRegH265d;
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typedef struct Vdpu34xRegH265dAddr_t {
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struct SWREG160_VP9_DELTA_PROB_BASE {
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RK_U32 vp9_delta_prob_base : 32;
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} reg160_no_use;
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RK_U32 reg161_pps_base;
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RK_U32 reg162_no_use;
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RK_U32 reg163_rps_base;
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RK_U32 reg164_179_ref_base[16];
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RK_U32 reg180_scanlist_addr;
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RK_U32 reg181_196_colmv_base[16];
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RK_U32 reg197_cabactbl_base;
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} Vdpu34xRegH265dAddr;
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typedef struct Vdpu34xH265dHighPoc_t {
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/* SWREG200 */
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struct SWREG200_REF0_7_POC_HIGHBIT {
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RK_U32 ref0_poc_highbit : 4;
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RK_U32 ref1_poc_highbit : 4;
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RK_U32 ref2_poc_highbit : 4;
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RK_U32 ref3_poc_highbit : 4;
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RK_U32 ref4_poc_highbit : 4;
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RK_U32 ref5_poc_highbit : 4;
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RK_U32 ref6_poc_highbit : 4;
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RK_U32 ref7_poc_highbit : 4;
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} reg200;
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struct SWREG201_REF8_15_POC_HIGHBIT {
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RK_U32 ref8_poc_highbit : 4;
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RK_U32 ref9_poc_highbit : 4;
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RK_U32 ref10_poc_highbit : 4;
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RK_U32 ref11_poc_highbit : 4;
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RK_U32 ref12_poc_highbit : 4;
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RK_U32 ref13_poc_highbit : 4;
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RK_U32 ref14_poc_highbit : 4;
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RK_U32 ref15_poc_highbit : 4;
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} reg201;
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struct SWREG200_REF16_23_POC_HIGHBIT {
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RK_U32 ref16_poc_highbit : 4;
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RK_U32 ref17_poc_highbit : 4;
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RK_U32 ref18_poc_highbit : 4;
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RK_U32 ref19_poc_highbit : 4;
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RK_U32 ref20_poc_highbit : 4;
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RK_U32 ref21_poc_highbit : 4;
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RK_U32 ref22_poc_highbit : 4;
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RK_U32 ref23_poc_highbit : 4;
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} reg202;
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struct SWREG200_REF24_31_POC_HIGHBIT {
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RK_U32 ref24_poc_highbit : 4;
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RK_U32 ref25_poc_highbit : 4;
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RK_U32 ref26_poc_highbit : 4;
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RK_U32 ref27_poc_highbit : 4;
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RK_U32 ref28_poc_highbit : 4;
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RK_U32 ref29_poc_highbit : 4;
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RK_U32 ref30_poc_highbit : 4;
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RK_U32 ref31_poc_highbit : 4;
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} reg203;
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struct SWREG200_CUR_POC_HIGHBIT {
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RK_U32 cur_poc_highbit : 4;
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RK_U32 reserver : 28;
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} reg204;
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} Vdpu34xH2645HighPoc_t;
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typedef struct Vdpu34xH265dRegSet_t {
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Vdpu34xRegCommon common;
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Vdpu34xRegH265d h265d_param;
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Vdpu34xRegCommonAddr common_addr;
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Vdpu34xRegH265dAddr h265d_addr;
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Vdpu34xH2645HighPoc_t highpoc;
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Vdpu34xRegIrqStatus irq_status;
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Vdpu34xRegStatistic statistic;
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} Vdpu34xH265dRegSet;
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#endif /* __VDPU34X_H265D_H__ */
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