/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __VDPU34X_COM_H__
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#define __VDPU34X_COM_H__
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#include "mpp_device.h"
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#include "vdpu34x.h"
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#define OFFSET_COMMON_REGS (8 * sizeof(RK_U32))
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#define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(RK_U32))
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#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32))
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#define OFFSET_CODEC_ADDR_REGS (160 * sizeof(RK_U32))
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#define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(RK_U32))
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#define OFFSET_INTERRUPT_REGS (224 * sizeof(RK_U32))
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#define OFFSET_STATISTIC_REGS (256 * sizeof(RK_U32))
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#define RCB_ALLINE_SIZE (64)
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#define MPP_RCB_BYTES(bits) MPP_ALIGN((bits + 7) / 8, RCB_ALLINE_SIZE)
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typedef enum Vdpu34x_RCB_TYPE_E {
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RCB_DBLK_ROW,
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RCB_INTRA_ROW,
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RCB_TRANSD_ROW,
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RCB_STRMD_ROW,
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RCB_INTER_ROW,
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RCB_SAO_ROW,
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RCB_FBC_ROW,
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RCB_TRANSD_COL,
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RCB_INTER_COL,
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RCB_FILT_COL,
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RCB_BUF_COUNT,
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} Vdpu34xRcbType_e;
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/* base: OFFSET_COMMON_REGS */
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typedef struct Vdpu34xRegCommon_t {
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struct SWREG8_IN_OUT {
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RK_U32 in_endian : 1;
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RK_U32 in_swap32_e : 1;
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RK_U32 in_swap64_e : 1;
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RK_U32 str_endian : 1;
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RK_U32 str_swap32_e : 1;
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RK_U32 str_swap64_e : 1;
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RK_U32 out_endian : 1;
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RK_U32 out_swap32_e : 1;
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RK_U32 out_cbcr_swap : 1;
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RK_U32 reserve : 23;
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} reg008;
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struct SWREG9_DEC_MODE {
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RK_U32 dec_mode : 10;
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RK_U32 reserve : 22;
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} reg009;
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struct SWREG10_DEC_E {
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RK_U32 dec_e : 1;
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RK_U32 reserve : 31;
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} reg010;
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struct SWREG11_IMPORTANT_EN {
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RK_U32 reserver : 1;
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RK_U32 dec_clkgate_e : 1;
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RK_U32 dec_e_strmd_clkgate_dis : 1;
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RK_U32 reserve0 : 1;
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RK_U32 dec_irq_dis : 1;
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RK_U32 dec_timeout_e : 1;
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RK_U32 buf_empty_en : 1;
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RK_U32 reserve1 : 3;
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RK_U32 dec_e_rewrite_valid : 1;
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RK_U32 reserve2 : 9;
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RK_U32 softrst_en_p : 1;
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RK_U32 force_softreset_valid : 1;
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RK_U32 reserve3 : 2;
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RK_U32 pix_range_detection_e : 1;
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RK_U32 reserve4 : 7;
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} reg011;
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struct SWREG12_SENCODARY_EN {
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RK_U32 wr_ddr_align_en : 1;
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RK_U32 colmv_compress_en : 1;
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RK_U32 fbc_e : 1;
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RK_U32 reserve0 : 1;
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RK_U32 buspr_slot_disable : 1;
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RK_U32 error_info_en : 1;
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RK_U32 info_collect_en : 1;
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RK_U32 wait_reset_en : 1;
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RK_U32 scanlist_addr_valid_en : 1;
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RK_U32 reserve1 : 23;
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} reg012;
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struct SWREG13_EN_MODE_SET {
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RK_U32 timeout_mode : 1;
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RK_U32 req_timeout_rst_sel : 1;
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RK_U32 reserve0 : 1;
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RK_U32 dec_commonirq_mode : 1;
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RK_U32 reserve1 : 2;
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RK_U32 stmerror_waitdecfifo_empty : 1;
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RK_U32 reserve2 : 2;
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RK_U32 h26x_streamd_error_mode : 1;
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RK_U32 reserve3 : 2;
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RK_U32 allow_not_wr_unref_bframe : 1;
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RK_U32 fbc_output_wr_disable : 1;
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RK_U32 reserve4 : 1;
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RK_U32 colmv_error_mode : 1;
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RK_U32 reserve5 : 2;
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RK_U32 h26x_error_mode : 1;
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RK_U32 reserve6 : 2;
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RK_U32 ycacherd_prior : 1;
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RK_U32 reserve7 : 2;
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RK_U32 cur_pic_is_idr : 1;
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RK_U32 reserve8 : 1;
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RK_U32 right_auto_rst_disable : 1;
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RK_U32 frame_end_err_rst_flag : 1;
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RK_U32 rd_prior_mode : 1;
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RK_U32 rd_ctrl_prior_mode : 1;
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RK_U32 reserve9 : 1;
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RK_U32 filter_outbuf_mode : 1;
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} reg013;
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struct SWREG14_FBC_PARAM_SET {
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RK_U32 fbc_force_uncompress : 1;
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RK_U32 reserve0 : 2;
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RK_U32 allow_16x8_cp_flag : 1;
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RK_U32 reserve1 : 2;
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RK_U32 fbc_h264_exten_4or8_flag: 1;
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RK_U32 reserve2 : 25;
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} reg014;
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struct SWREG15_STREAM_PARAM_SET {
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RK_U32 rlc_mode_direct_write : 1;
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RK_U32 rlc_mode : 1;
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RK_U32 reserve0 : 3;
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RK_U32 strm_start_bit : 7;
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RK_U32 reserve1 : 20;
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} reg015;
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RK_U32 reg016_str_len;
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struct SWREG17_SLICE_NUMBER {
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RK_U32 slice_num : 25;
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RK_U32 reserve : 7;
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} reg017;
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struct SWREG18_Y_HOR_STRIDE {
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RK_U32 y_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg018;
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struct SWREG19_UV_HOR_STRIDE {
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RK_U32 uv_hor_virstride : 16;
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RK_U32 reserve : 16;
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} reg019;
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union {
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struct SWREG20_Y_STRIDE {
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RK_U32 y_virstride : 28;
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RK_U32 reserve : 4;
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} reg020_y_virstride;
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struct SWREG20_FBC_PAYLOAD_OFFSET {
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RK_U32 reserve : 4;
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RK_U32 payload_st_offset : 28;
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} reg020_fbc_payload_off;
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};
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struct SWREG21_ERROR_CTRL_SET {
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RK_U32 inter_error_prc_mode : 1;
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RK_U32 error_intra_mode : 1;
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RK_U32 error_deb_en : 1;
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RK_U32 picidx_replace : 5;
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RK_U32 reserve0 : 16;
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RK_U32 roi_error_ctu_cal_en : 1;
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RK_U32 reserve1 : 7;
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} reg021;
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struct SWREG22_ERR_ROI_CTU_OFFSET_START {
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RK_U32 roi_x_ctu_offset_st : 12;
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RK_U32 reserve0 : 4;
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RK_U32 roi_y_ctu_offset_st : 12;
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RK_U32 reserve1 : 4;
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} reg022;
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struct SWREG23_ERR_ROI_CTU_OFFSET_END {
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RK_U32 roi_x_ctu_offset_end : 12;
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RK_U32 reserve0 : 4;
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RK_U32 roi_y_ctu_offset_end : 12;
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RK_U32 reserve1 : 4;
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} reg023;
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struct SWREG24_CABAC_ERROR_EN_LOWBITS {
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RK_U32 cabac_err_en_lowbits : 32;
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} reg024;
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struct SWREG25_CABAC_ERROR_EN_HIGHBITS {
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RK_U32 cabac_err_en_highbits : 30;
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RK_U32 reserve : 2;
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} reg025;
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struct SWREG26_BLOCK_GATING_EN {
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RK_U32 swreg_block_gating_e : 20;
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RK_U32 reserve : 11;
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RK_U32 reg_cfg_gating_en : 1;
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} reg026;
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RK_U32 reg027;
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struct SWREG28_MULTIPLY_CORE_CTRL {
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RK_U32 swreg_vp9_wr_prob_idx : 3;
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RK_U32 reserve0 : 1;
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RK_U32 swreg_vp9_rd_prob_idx : 3;
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RK_U32 reserve1 : 1;
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RK_U32 swreg_ref_req_advance_flag : 1;
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RK_U32 sw_colmv_req_advance_flag : 1;
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RK_U32 sw_poc_only_highbit_flag : 1;
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RK_U32 sw_poc_arb_flag : 1;
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RK_U32 reserve2 : 4;
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RK_U32 sw_film_idx : 10;
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RK_U32 reserve3 : 2;
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RK_U32 sw_pu_req_mismatch_dis : 1;
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RK_U32 sw_colmv_req_mismatch_dis : 1;
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RK_U32 reserve4 : 2;
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} reg028;
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/* NOTE: reg027 ~ reg032 are added in vdpu38x at rk3588 */
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RK_U32 reg029_031[3];
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/* NOTE: timeout must be config in vdpu38x */
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RK_U32 reg032_timeout_threshold;
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} Vdpu34xRegCommon;
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/* base: OFFSET_COMMON_ADDR_REGS */
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typedef struct Vdpu34xRegCommonAddr_t {
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/* offset 128 */
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RK_U32 reg128_rlc_base;
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RK_U32 reg129_rlcwrite_base;
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RK_U32 reg130_decout_base;
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RK_U32 reg131_colmv_cur_base;
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RK_U32 reg132_error_ref_base;
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RK_U32 reg133_rcb_intra_base;
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RK_U32 reg134_rcb_transd_row_base;
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RK_U32 reg135_rcb_transd_col_base;
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RK_U32 reg136_rcb_streamd_row_base;
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RK_U32 reg137_rcb_inter_row_base;
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RK_U32 reg138_rcb_inter_col_base;
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RK_U32 reg139_rcb_dblk_base;
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RK_U32 reg140_rcb_sao_base;
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RK_U32 reg141_rcb_fbc_base;
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RK_U32 reg142_rcb_filter_col_base;
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} Vdpu34xRegCommonAddr;
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/* base: OFFSET_COMMON_ADDR_REGS */
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typedef struct Vdpu34xRegIrqStatus_t {
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struct SWREG224_STA_INT {
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RK_U32 dec_irq : 1;
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RK_U32 dec_irq_raw : 1;
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RK_U32 dec_rdy_sta : 1;
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RK_U32 dec_bus_sta : 1;
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RK_U32 dec_error_sta : 1;
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RK_U32 dec_timeout_sta : 1;
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RK_U32 buf_empty_sta : 1;
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RK_U32 colmv_ref_error_sta : 1;
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RK_U32 cabu_end_sta : 1;
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RK_U32 softreset_rdy : 1;
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RK_U32 reserve : 22;
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} reg224;
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struct SWREG225_STA_ERR_INFO {
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RK_U32 all_frame_error_flag : 1;
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RK_U32 strmd_detect_error_flag : 1;
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RK_U32 reserve : 30;
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} reg225;
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struct SWREG226_STA_CABAC_ERROR_STATUS {
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RK_U32 strmd_error_status : 28;
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RK_U32 reserve : 4;
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} reg226;
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struct SWREG227_STA_COLMV_ERROR_REF_PICIDX {
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RK_U32 colmv_error_ref_picidx : 4;
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RK_U32 reserve : 28;
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} reg227;
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struct SWREG228_STA_CABAC_ERROR_CTU_OFFSET {
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RK_U32 cabac_error_ctu_offset : 32;
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} reg228;
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struct SWREG229_STA_SAOWR_CTU_OFFSET {
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RK_U32 saowr_xoffset : 16;
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RK_U32 saowr_yoffset : 16;
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} reg229;
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struct SWREG230_STA_SLICE_DEC_NUM {
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RK_U32 slicedec_num : 25;
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RK_U32 reserve : 7;
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} reg230;
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struct SWREG231_STA_FRAME_ERROR_CTU_NUM {
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RK_U32 frame_ctu_err_num : 32;
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} reg231;
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struct SWREG232_STA_ERROR_PACKET_NUM {
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RK_U32 packet_err_num : 16;
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RK_U32 reserve : 16;
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} reg232;
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struct SWREG233_STA_ERR_CTU_NUM_IN_RO {
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RK_U32 error_ctu_num_in_roi : 24;
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RK_U32 reserve : 8;
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} reg233;
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RK_U32 reserve_reg234_237[4];
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} Vdpu34xRegIrqStatus;
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typedef struct Vdpu34xRegStatistic_t {
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struct SWREG256_DEBUG_PERF_LATENCY_CTRL0 {
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RK_U32 axi_perf_work_e : 1;
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RK_U32 axi_perf_clr_e : 1;
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RK_U32 reserve0 : 1;
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RK_U32 axi_cnt_type : 1;
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RK_U32 rd_latency_id : 4;
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RK_U32 rd_latency_thr : 12;
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RK_U32 reserve1 : 12;
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} reg256;
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struct SWREG257_DEBUG_PERF_LATENCY_CTRL1 {
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RK_U32 addr_align_type : 2;
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RK_U32 ar_cnt_id_type : 1;
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RK_U32 aw_cnt_id_type : 1;
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RK_U32 ar_count_id : 4;
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RK_U32 aw_count_id : 4;
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RK_U32 rd_band_width_mode : 1;
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RK_U32 reserve : 19;
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} reg257;
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struct SWREG258_DEBUG_PERF_RD_MAX_LATENCY_NUM {
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RK_U32 rd_max_latency_num : 16;
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RK_U32 reserve : 16;
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} reg258;
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RK_U32 reg259_rd_latency_thr_num_ch0;
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RK_U32 reg260_rd_latency_acc_sum;
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RK_U32 reg261_perf_rd_axi_total_byte;
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RK_U32 reg262_perf_wr_axi_total_byte;
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RK_U32 reg263_perf_working_cnt;
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RK_U32 reserve_reg264;
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struct SWREG265_DEBUG_PERF_SEL {
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RK_U32 perf_cnt0_sel : 6;
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RK_U32 reserve0 : 2;
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RK_U32 perf_cnt1_sel : 6;
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RK_U32 reserve1 : 2;
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RK_U32 perf_cnt2_sel : 6;
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RK_U32 reserve2 : 10;
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} reg265;
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RK_U32 reg266_perf_cnt0;
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RK_U32 reg267_perf_cnt1;
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RK_U32 reg268_perf_cnt2;
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RK_U32 reserve_reg269;
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struct SWREG270_DEBUG_QOS_CTRL {
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RK_U32 bus2mc_buffer_qos_level : 8;
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RK_U32 reserve0 : 8;
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RK_U32 axi_rd_hurry_level : 2;
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RK_U32 reserve1 : 2;
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RK_U32 axi_wr_qos : 2;
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RK_U32 reserve2 : 2;
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RK_U32 axi_wr_hurry_level : 2;
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RK_U32 reserve3 : 2;
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RK_U32 axi_rd_qos : 2;
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RK_U32 reserve4 : 2;
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} reg270;
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RK_U32 reg271_wr_wait_cycle_qos;
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struct SWREG272_DEBUG_INT {
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RK_U32 bu_rw_clean : 1;
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RK_U32 saowr_frame_rdy : 1;
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RK_U32 saobu_frame_rdy_valid : 1;
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RK_U32 colmvwr_frame_rdy_real : 1;
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RK_U32 cabu_rlcend_valid_real : 1;
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RK_U32 stream_rdburst_cnteq0_towr : 1;
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RK_U32 wr_tansfer_cnt : 6;
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RK_U32 reserve0 : 4;
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RK_U32 streamfifo_space2full : 7;
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RK_U32 reserve1 : 9;
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} reg272;
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struct SWREG273 {
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RK_U32 bus_status_flag : 19;
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RK_U32 reserve0 : 12;
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RK_U32 pps_no_ref_bframe_dec_r : 1;
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} reg273;
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RK_U16 reg274_y_min_value;
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RK_U16 reg274_y_max_value;
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RK_U16 reg275_u_min_value;
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RK_U16 reg275_u_max_value;
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RK_U16 reg276_v_min_value;
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RK_U16 reg276_v_max_value;
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} Vdpu34xRegStatistic;
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typedef struct vdpu34x_rcb_info_t {
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RK_S32 reg;
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RK_S32 size;
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RK_S32 offset;
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} Vdpu34xRcbInfo;
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#ifdef __cplusplus
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extern "C" {
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#endif
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RK_S32 get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height);
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void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info);
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RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b);
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void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __VDPU34X_COM_H__ */
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