/*
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*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* @file hal_h265d_reg.h
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* @brief
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* @author csy(csy@rock-chips.com)
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* @version 1.0.0
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* @history
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* 2015.7.15 : Create
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*/
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#ifndef __HAL_H265D_REG_H__
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#define __HAL_H265D_REG_H__
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#include "rk_type.h"
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#define HEVC_DECODER_REG_NUM (48)
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#define RKVDEC_REG_PERF_CYCLE_INDEX (64)
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#define RKVDEC_HEVC_REGISTERS (68)
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#define RKVDEC_V1_REGISTERS (78)
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#define V345_HEVC_REGISTERS (108)
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typedef struct RKV_HEVC_REG_END {
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RK_U32 performance_cycle; //65
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RK_U32 axi_ddr_rdata;
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RK_U32 axi_ddr_wdata;
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RK_U32 fpgadebug_reset;
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RK_U32 reserve[9];
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RK_U32 extern_error_en;
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} rkv_reg_end;
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typedef struct V345_HEVC_REG_END {
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struct hevc_mvc0 {
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RK_U32 refp_layer_same_with_cur : 16 ;
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RK_U32 reserve : 16 ;
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} reg064_mvc0;
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RK_U32 reserve[55];
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} v345_reg_end;
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typedef struct {
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struct swreg_id {
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RK_U32 minor_ver : 8 ;
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RK_U32 major_ver : 8 ;
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RK_U32 prod_num : 16 ;
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} sw_id;
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struct swreg_int {
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RK_U32 sw_dec_e : 1 ;
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RK_U32 sw_dec_clkgate_e : 1 ;
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RK_U32 reserve0 : 2 ;
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RK_U32 sw_dec_irq_dis : 1 ;
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RK_U32 sw_dec_timeout_e : 1 ;
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RK_U32 sw_buf_empty_en : 1 ;
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RK_U32 reserve1 : 1 ;
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RK_U32 sw_dec_irq : 1 ;
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RK_U32 sw_dec_irq_raw : 1 ;
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RK_U32 reserve2 : 2 ;
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RK_U32 sw_dec_rdy_sta : 1 ;
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RK_U32 sw_dec_bus_sta : 1 ;
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RK_U32 sw_dec_error_sta : 1 ;
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RK_U32 sw_dec_timeout_sta : 1 ;
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RK_U32 sw_dec_empty_sta : 1 ;
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RK_U32 reserve4 : 3 ;
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RK_U32 sw_softrst_en_p : 1 ;
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RK_U32 sw_force_softreset_valid: 1 ;
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RK_U32 sw_softreset_rdy : 1 ;
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RK_U32 sw_wr_ddr_align_en : 1;
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RK_U32 sw_scl_down_en : 1;
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RK_U32 sw_allow_not_wr_unref_bframe : 1;
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} sw_interrupt; ///<- zrh: do nothing in C Model
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struct swreg_sysctrl {
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RK_U32 sw_in_endian : 1 ;
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RK_U32 sw_in_swap32_e : 1 ;
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RK_U32 sw_in_swap64_e : 1 ;
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RK_U32 sw_str_endian : 1 ;
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RK_U32 sw_str_swap32_e : 1 ;
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RK_U32 sw_str_swap64_e : 1 ;
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RK_U32 sw_out_endian : 1 ;
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RK_U32 sw_out_swap32_e : 1 ;
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RK_U32 sw_out_cbcr_swap : 1 ;
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RK_U32 sw_error_info_en : 1 ;
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RK_U32 sw_rlc_mode_direct_write : 1;
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RK_U32 sw_rlc_mode : 1 ;
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RK_U32 sw_strm_start_bit : 7 ;
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RK_U32 sw_inter_error_prc_mode : 1;
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RK_U32 sw_dec_mode : 2 ;
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RK_U32 sw_info_collect_en : 1 ;
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RK_U32 sw_wait_reset_en : 1 ;
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RK_U32 sw_h26x_rps_mode : 1 ;
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RK_U32 reserve2 : 5 ;
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RK_U32 sw_colmv_mode : 1 ;
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RK_U32 sw_head_prior_high_en : 1;
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} sw_sysctrl;
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struct swreg_pic {
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RK_U32 sw_y_hor_virstride : 9 ;
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RK_U32 reserve : 3 ;
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RK_U32 sw_uv_hor_virstride : 9 ;
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RK_U32 sw_slice_num : 8 ;
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} sw_picparameter;
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RK_U32 sw_strm_rlc_base ;///<- zrh: do nothing in C Model
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RK_U32 sw_stream_len ;///<- zrh: do nothing in C Model
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RK_U32 sw_cabactbl_base ;///<- zrh: do nothing in C Model
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RK_U32 sw_decout_base ;
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RK_U32 sw_y_virstride ;
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RK_U32 sw_yuv_virstride ;
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RK_U32 sw_refer_base[15] ;
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RK_S32 sw_refer_poc[15] ;
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RK_S32 sw_cur_poc ;
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RK_U32 sw_rlcwrite_base ;///<- zrh: do nothing in C Model
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RK_U32 sw_pps_base ;///<- zrh: do nothing in C Model
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RK_U32 sw_rps_base ;///<- zrh: do nothing in C Model
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RK_U32 cabac_error_en ;///<- zrh add
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RK_U32 cabac_error_status ;///<- zrh add
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struct cabac_error_ctu {
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RK_U32 sw_cabac_error_ctu_xoffset : 8;
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RK_U32 sw_cabac_error_ctu_yoffset : 8;
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RK_U32 sw_streamfifo_space2full : 7;
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RK_U32 reversed0 : 9;
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} cabac_error_ctu;
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struct sao_ctu_position {
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RK_U32 sw_saowr_xoffset : 9;
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RK_U32 reversed0 : 7;
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RK_U32 sw_saowr_yoffset : 10;
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RK_U32 reversed1 : 6;
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} sao_ctu_position;
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RK_U32 reg_not_use0[RKVDEC_REG_PERF_CYCLE_INDEX - HEVC_DECODER_REG_NUM];
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union {
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rkv_reg_end rkv_reg_ends;
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v345_reg_end v345_reg_ends;
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};
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} H265d_REGS_t;
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#endif
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