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<title>GNU Compiler Collection (GCC) Internals: Looping Patterns</title>
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<a name="Looping-Patterns"></a>
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<div class="header">
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<p>
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Next: <a href="Insn-Canonicalizations.html#Insn-Canonicalizations" accesskey="n" rel="next">Insn Canonicalizations</a>, Previous: <a href="Jump-Patterns.html#Jump-Patterns" accesskey="p" rel="prev">Jump Patterns</a>, Up: <a href="Machine-Desc.html#Machine-Desc" accesskey="u" rel="up">Machine Desc</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="Defining-Looping-Instruction-Patterns"></a>
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<h3 class="section">16.13 Defining Looping Instruction Patterns</h3>
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<a name="index-looping-instruction-patterns"></a>
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<a name="index-defining-looping-instruction-patterns"></a>
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<p>Some machines have special jump instructions that can be utilized to
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make loops more efficient. A common example is the 68000 ‘<samp>dbra</samp>’
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instruction which performs a decrement of a register and a branch if the
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result was greater than zero. Other machines, in particular digital
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signal processors (DSPs), have special block repeat instructions to
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provide low-overhead loop support. For example, the TI TMS320C3x/C4x
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DSPs have a block repeat instruction that loads special registers to
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mark the top and end of a loop and to count the number of loop
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iterations. This avoids the need for fetching and executing a
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‘<samp>dbra</samp>’-like instruction and avoids pipeline stalls associated with
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the jump.
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</p>
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<p>GCC has three special named patterns to support low overhead looping.
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They are ‘<samp>decrement_and_branch_until_zero</samp>’, ‘<samp>doloop_begin</samp>’,
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and ‘<samp>doloop_end</samp>’. The first pattern,
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‘<samp>decrement_and_branch_until_zero</samp>’, is not emitted during RTL
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generation but may be emitted during the instruction combination phase.
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This requires the assistance of the loop optimizer, using information
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collected during strength reduction, to reverse a loop to count down to
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zero. Some targets also require the loop optimizer to add a
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<code>REG_NONNEG</code> note to indicate that the iteration count is always
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positive. This is needed if the target performs a signed loop
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termination test. For example, the 68000 uses a pattern similar to the
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following for its <code>dbra</code> instruction:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_insn "decrement_and_branch_until_zero"
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[(set (pc)
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(if_then_else
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(ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
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(const_int -1))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(plus:SI (match_dup 0)
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(const_int -1)))]
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"find_reg_note (insn, REG_NONNEG, 0)"
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"…")
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</pre></div>
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<p>Note that since the insn is both a jump insn and has an output, it must
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deal with its own reloads, hence the ‘m’ constraints. Also note that
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since this insn is generated by the instruction combination phase
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combining two sequential insns together into an implicit parallel insn,
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the iteration counter needs to be biased by the same amount as the
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decrement operation, in this case -1. Note that the following similar
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pattern will not be matched by the combiner.
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_insn "decrement_and_branch_until_zero"
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[(set (pc)
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(if_then_else
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(ge (match_operand:SI 0 "general_operand" "+d*am")
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(const_int 1))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_dup 0)
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(plus:SI (match_dup 0)
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(const_int -1)))]
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"find_reg_note (insn, REG_NONNEG, 0)"
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"…")
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</pre></div>
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<p>The other two special looping patterns, ‘<samp>doloop_begin</samp>’ and
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‘<samp>doloop_end</samp>’, are emitted by the loop optimizer for certain
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well-behaved loops with a finite number of loop iterations using
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information collected during strength reduction.
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</p>
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<p>The ‘<samp>doloop_end</samp>’ pattern describes the actual looping instruction
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(or the implicit looping operation) and the ‘<samp>doloop_begin</samp>’ pattern
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is an optional companion pattern that can be used for initialization
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needed for some low-overhead looping instructions.
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</p>
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<p>Note that some machines require the actual looping instruction to be
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emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
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the true RTL for a looping instruction at the top of the loop can cause
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problems with flow analysis. So instead, a dummy <code>doloop</code> insn is
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emitted at the end of the loop. The machine dependent reorg pass checks
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for the presence of this <code>doloop</code> insn and then searches back to
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the top of the loop, where it inserts the true looping insn (provided
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there are no instructions in the loop which would cause problems). Any
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additional labels can be emitted at this point. In addition, if the
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desired special iteration counter register was not allocated, this
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machine dependent reorg pass could emit a traditional compare and jump
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instruction pair.
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</p>
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<p>The essential difference between the
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‘<samp>decrement_and_branch_until_zero</samp>’ and the ‘<samp>doloop_end</samp>’
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patterns is that the loop optimizer allocates an additional pseudo
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register for the latter as an iteration counter. This pseudo register
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cannot be used within the loop (i.e., general induction variables cannot
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be derived from it), however, in many cases the loop induction variable
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may become redundant and removed by the flow pass.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Insn-Canonicalizations.html#Insn-Canonicalizations" accesskey="n" rel="next">Insn Canonicalizations</a>, Previous: <a href="Jump-Patterns.html#Jump-Patterns" accesskey="p" rel="prev">Jump Patterns</a>, Up: <a href="Machine-Desc.html#Machine-Desc" accesskey="u" rel="up">Machine Desc</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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