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<title>Using as: s390 Options</title>
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<a name="s390-Options"></a>
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Next: <a href="s390-Characters.html#s390-Characters" accesskey="n" rel="next">s390 Characters</a>, Up: <a href="S_002f390_002dDependent.html#S_002f390_002dDependent" accesskey="u" rel="up">S/390-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<a name="Options-19"></a>
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<h4 class="subsection">9.38.1 Options</h4>
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<a name="index-options-for-s390"></a>
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<a name="index-s390-options"></a>
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<p>The following table lists all available s390 specific options:
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</p>
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<dl compact="compact">
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<dd><a name="index-_002dm31-option_002c-s390"></a>
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<a name="index-_002dm64-option_002c-s390"></a>
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</dd>
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<dt><code>-m31 | -m64</code></dt>
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<dd><p>Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
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</p>
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<p>These options are only available with the ELF object file format, and
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require that the necessary BFD support has been included (on a 31-bit
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platform you must add –enable-64-bit-bfd on the call to the configure
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script to enable 64-bit usage and use s390x as target platform).
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</p>
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<a name="index-_002dmesa-option_002c-s390"></a>
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<a name="index-_002dmzarch-option_002c-s390"></a>
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</dd>
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<dt><code>-mesa | -mzarch</code></dt>
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<dd><p>Select the architecture mode, either the Enterprise System Architecture
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(esa) mode or the z/Architecture mode (zarch).
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</p>
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<p>The 64-bit instructions are only available with the z/Architecture mode.
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The combination of ‘<samp>-m64</samp>’ and ‘<samp>-mesa</samp>’ results in a warning
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message.
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</p>
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<a name="index-_002dmarch_003d-option_002c-s390"></a>
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</dd>
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<dt><code>-march=<var>CPU</var></code></dt>
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<dd><p>This option specifies the target processor. The following processor names
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are recognized:
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<code>g5</code>,
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<code>g6</code>,
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<code>z900</code>,
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<code>z990</code>,
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<code>z9-109</code>,
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<code>z9-ec</code>,
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<code>z10</code>,
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<code>z196</code>,
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<code>zEC12</code>, and
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<code>z13</code>.
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Assembling an instruction that is not supported on the target processor
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results in an error message. Do not specify <code>g5</code> or <code>g6</code>
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with ‘<samp>-mzarch</samp>’.
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</p>
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<a name="index-_002dmregnames-option_002c-s390"></a>
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</dd>
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<dt><code>-mregnames</code></dt>
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<dd><p>Allow symbolic names for registers.
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</p>
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<a name="index-_002dmno_002dregnames-option_002c-s390"></a>
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</dd>
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<dt><code>-mno-regnames</code></dt>
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<dd><p>Do not allow symbolic names for registers.
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</p>
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<a name="index-_002dmwarn_002dareg_002dzero-option_002c-s390"></a>
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</dd>
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<dt><code>-mwarn-areg-zero</code></dt>
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<dd><p>Warn whenever the operand for a base or index register has been specified
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but evaluates to zero. This can indicate the misuse of general purpose
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register 0 as an address register.
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</p>
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</dd>
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