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<title>Using as: i386-Variations</title>
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<a name="i386_002dVariations"></a>
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<div class="header">
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<p>
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Next: <a href="i386_002dChars.html#i386_002dChars" accesskey="n" rel="next">i386-Chars</a>, Up: <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="u" rel="up">i386-Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="AT_0026T-Syntax-versus-Intel-Syntax"></a>
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<h4 class="subsubsection">9.15.3.1 AT&T Syntax versus Intel Syntax</h4>
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<a name="index-i386-intel_005fsyntax-pseudo-op"></a>
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<a name="index-intel_005fsyntax-pseudo-op_002c-i386"></a>
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<a name="index-i386-att_005fsyntax-pseudo-op"></a>
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<a name="index-att_005fsyntax-pseudo-op_002c-i386"></a>
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<a name="index-i386-syntax-compatibility"></a>
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<a name="index-syntax-compatibility_002c-i386"></a>
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<a name="index-x86_002d64-intel_005fsyntax-pseudo-op"></a>
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<a name="index-intel_005fsyntax-pseudo-op_002c-x86_002d64"></a>
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<a name="index-x86_002d64-att_005fsyntax-pseudo-op"></a>
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<a name="index-att_005fsyntax-pseudo-op_002c-x86_002d64"></a>
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<a name="index-x86_002d64-syntax-compatibility"></a>
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<a name="index-syntax-compatibility_002c-x86_002d64"></a>
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<p><code>as</code> now supports assembly using Intel assembler syntax.
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<code>.intel_syntax</code> selects Intel mode, and <code>.att_syntax</code> switches
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back to the usual AT&T mode for compatibility with the output of
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<code>gcc</code>. Either of these directives may have an optional
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argument, <code>prefix</code>, or <code>noprefix</code> specifying whether registers
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require a ‘<samp>%</samp>’ prefix. AT&T System V/386 assembler syntax is quite
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different from Intel syntax. We mention these differences because
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almost all 80386 documents use Intel syntax. Notable differences
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between the two syntaxes are:
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</p>
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<a name="index-immediate-operands_002c-i386"></a>
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<a name="index-i386-immediate-operands"></a>
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<a name="index-register-operands_002c-i386"></a>
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<a name="index-i386-register-operands"></a>
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<a name="index-jump_002fcall-operands_002c-i386"></a>
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<a name="index-i386-jump_002fcall-operands"></a>
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<a name="index-operand-delimiters_002c-i386"></a>
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<a name="index-immediate-operands_002c-x86_002d64"></a>
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<a name="index-x86_002d64-immediate-operands"></a>
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<a name="index-register-operands_002c-x86_002d64"></a>
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<a name="index-x86_002d64-register-operands"></a>
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<a name="index-jump_002fcall-operands_002c-x86_002d64"></a>
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<a name="index-x86_002d64-jump_002fcall-operands"></a>
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<a name="index-operand-delimiters_002c-x86_002d64"></a>
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<ul>
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<li> AT&T immediate operands are preceded by ‘<samp>$</samp>’; Intel immediate
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operands are undelimited (Intel ‘<samp>push 4</samp>’ is AT&T ‘<samp>pushl $4</samp>’).
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AT&T register operands are preceded by ‘<samp>%</samp>’; Intel register operands
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are undelimited. AT&T absolute (as opposed to PC relative) jump/call
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operands are prefixed by ‘<samp>*</samp>’; they are undelimited in Intel syntax.
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</li><li> <a name="index-i386-source_002c-destination-operands"></a>
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<a name="index-source_002c-destination-operands_003b-i386"></a>
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<a name="index-x86_002d64-source_002c-destination-operands"></a>
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<a name="index-source_002c-destination-operands_003b-x86_002d64"></a>
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AT&T and Intel syntax use the opposite order for source and destination
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operands. Intel ‘<samp>add eax, 4</samp>’ is ‘<samp>addl $4, %eax</samp>’. The
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‘<samp>source, dest</samp>’ convention is maintained for compatibility with
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previous Unix assemblers. Note that ‘<samp>bound</samp>’, ‘<samp>invlpga</samp>’, and
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instructions with 2 immediate operands, such as the ‘<samp>enter</samp>’
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instruction, do <em>not</em> have reversed order. <a href="i386_002dBugs.html#i386_002dBugs">i386-Bugs</a>.
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</li><li> <a name="index-mnemonic-suffixes_002c-i386"></a>
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<a name="index-sizes-operands_002c-i386"></a>
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<a name="index-i386-size-suffixes"></a>
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<a name="index-mnemonic-suffixes_002c-x86_002d64"></a>
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<a name="index-sizes-operands_002c-x86_002d64"></a>
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<a name="index-x86_002d64-size-suffixes"></a>
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In AT&T syntax the size of memory operands is determined from the last
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character of the instruction mnemonic. Mnemonic suffixes of ‘<samp>b</samp>’,
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‘<samp>w</samp>’, ‘<samp>l</samp>’ and ‘<samp>q</samp>’ specify byte (8-bit), word (16-bit), long
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(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes
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this by prefixing memory operands (<em>not</em> the instruction mnemonics) with
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‘<samp>byte ptr</samp>’, ‘<samp>word ptr</samp>’, ‘<samp>dword ptr</samp>’ and ‘<samp>qword ptr</samp>’. Thus,
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Intel ‘<samp>mov al, byte ptr <var>foo</var></samp>’ is ‘<samp>movb <var>foo</var>, %al</samp>’ in AT&T
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syntax.
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<p>In 64-bit code, ‘<samp>movabs</samp>’ can be used to encode the ‘<samp>mov</samp>’
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instruction with the 64-bit displacement or immediate operand.
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</p>
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</li><li> <a name="index-return-instructions_002c-i386"></a>
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<a name="index-i386-jump_002c-call_002c-return"></a>
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<a name="index-return-instructions_002c-x86_002d64"></a>
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<a name="index-x86_002d64-jump_002c-call_002c-return"></a>
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Immediate form long jumps and calls are
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‘<samp>lcall/ljmp $<var>section</var>, $<var>offset</var></samp>’ in AT&T syntax; the
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Intel syntax is
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‘<samp>call/jmp far <var>section</var>:<var>offset</var></samp>’. Also, the far return
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instruction
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is ‘<samp>lret $<var>stack-adjust</var></samp>’ in AT&T syntax; Intel syntax is
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‘<samp>ret far <var>stack-adjust</var></samp>’.
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</li><li> <a name="index-sections_002c-i386"></a>
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<a name="index-i386-sections"></a>
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<a name="index-sections_002c-x86_002d64"></a>
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<a name="index-x86_002d64-sections"></a>
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The AT&T assembler does not provide support for multiple section
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programs. Unix style systems expect all programs to be single sections.
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</li></ul>
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<hr>
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<div class="header">
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<p>
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Next: <a href="i386_002dChars.html#i386_002dChars" accesskey="n" rel="next">i386-Chars</a>, Up: <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="u" rel="up">i386-Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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